1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2016 Marvell Technology Group Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device Tree file for Marvell Armada AP806. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "armada-ap806.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Marvell Armada AP806 Dual"; 12*4882a593Smuzhiyun compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun cpus { 15*4882a593Smuzhiyun #address-cells = <1>; 16*4882a593Smuzhiyun #size-cells = <0>; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun cpu0: cpu@0 { 19*4882a593Smuzhiyun device_type = "cpu"; 20*4882a593Smuzhiyun compatible = "arm,cortex-a72"; 21*4882a593Smuzhiyun reg = <0x000>; 22*4882a593Smuzhiyun enable-method = "psci"; 23*4882a593Smuzhiyun #cooling-cells = <2>; 24*4882a593Smuzhiyun clocks = <&cpu_clk 0>; 25*4882a593Smuzhiyun i-cache-size = <0xc000>; 26*4882a593Smuzhiyun i-cache-line-size = <64>; 27*4882a593Smuzhiyun i-cache-sets = <256>; 28*4882a593Smuzhiyun d-cache-size = <0x8000>; 29*4882a593Smuzhiyun d-cache-line-size = <64>; 30*4882a593Smuzhiyun d-cache-sets = <256>; 31*4882a593Smuzhiyun next-level-cache = <&l2>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun cpu1: cpu@1 { 34*4882a593Smuzhiyun device_type = "cpu"; 35*4882a593Smuzhiyun compatible = "arm,cortex-a72"; 36*4882a593Smuzhiyun reg = <0x001>; 37*4882a593Smuzhiyun enable-method = "psci"; 38*4882a593Smuzhiyun #cooling-cells = <2>; 39*4882a593Smuzhiyun clocks = <&cpu_clk 0>; 40*4882a593Smuzhiyun i-cache-size = <0xc000>; 41*4882a593Smuzhiyun i-cache-line-size = <64>; 42*4882a593Smuzhiyun i-cache-sets = <256>; 43*4882a593Smuzhiyun d-cache-size = <0x8000>; 44*4882a593Smuzhiyun d-cache-line-size = <64>; 45*4882a593Smuzhiyun d-cache-sets = <256>; 46*4882a593Smuzhiyun next-level-cache = <&l2>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun l2: l2-cache { 50*4882a593Smuzhiyun compatible = "cache"; 51*4882a593Smuzhiyun cache-size = <0x80000>; 52*4882a593Smuzhiyun cache-line-size = <64>; 53*4882a593Smuzhiyun cache-sets = <512>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun thermal-zones { 58*4882a593Smuzhiyun /delete-node/ ap-thermal-cpu2; 59*4882a593Smuzhiyun /delete-node/ ap-thermal-cpu3; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62