1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2017 Marvell Technology Group Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device Tree file for the Armada 70x0 SoC 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun aliases { 10*4882a593Smuzhiyun gpio1 = &cp0_gpio1; 11*4882a593Smuzhiyun gpio2 = &cp0_gpio2; 12*4882a593Smuzhiyun spi1 = &cp0_spi0; 13*4882a593Smuzhiyun spi2 = &cp0_spi1; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/* 18*4882a593Smuzhiyun * Instantiate the CP110 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun#define CP11X_NAME cp0 21*4882a593Smuzhiyun#define CP11X_BASE f2000000 22*4882a593Smuzhiyun#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) 23*4882a593Smuzhiyun#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 24*4882a593Smuzhiyun#define CP11X_PCIE0_BASE f2600000 25*4882a593Smuzhiyun#define CP11X_PCIE1_BASE f2620000 26*4882a593Smuzhiyun#define CP11X_PCIE2_BASE f2640000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun#include "armada-cp110.dtsi" 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun#undef CP11X_NAME 31*4882a593Smuzhiyun#undef CP11X_BASE 32*4882a593Smuzhiyun#undef CP11X_PCIEx_MEM_BASE 33*4882a593Smuzhiyun#undef CP11X_PCIEx_MEM_SIZE 34*4882a593Smuzhiyun#undef CP11X_PCIE0_BASE 35*4882a593Smuzhiyun#undef CP11X_PCIE1_BASE 36*4882a593Smuzhiyun#undef CP11X_PCIE2_BASE 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun&cp0_gpio1 { 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&cp0_gpio2 { 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&cp0_syscon0 { 47*4882a593Smuzhiyun cp0_pinctrl: pinctrl { 48*4882a593Smuzhiyun compatible = "marvell,armada-7k-pinctrl"; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun nand_pins: nand-pins { 51*4882a593Smuzhiyun marvell,pins = 52*4882a593Smuzhiyun "mpp15", "mpp16", "mpp17", "mpp18", 53*4882a593Smuzhiyun "mpp19", "mpp20", "mpp21", "mpp22", 54*4882a593Smuzhiyun "mpp23", "mpp24", "mpp25", "mpp26", 55*4882a593Smuzhiyun "mpp27"; 56*4882a593Smuzhiyun marvell,function = "dev"; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun nand_rb: nand-rb { 60*4882a593Smuzhiyun marvell,pins = "mpp13"; 61*4882a593Smuzhiyun marvell,function = "nf"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun}; 65