1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2020 Compass Electronics Group, LLC 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun usdhc1_pwrseq: usdhc1_pwrseq { 8*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 9*4882a593Smuzhiyun pinctrl-names = "default"; 10*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc1_gpio>; 11*4882a593Smuzhiyun reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 12*4882a593Smuzhiyun clocks = <&osc_32k>; 13*4882a593Smuzhiyun clock-names = "ext_clock"; 14*4882a593Smuzhiyun post-power-on-delay-ms = <80>; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun memory@40000000 { 18*4882a593Smuzhiyun device_type = "memory"; 19*4882a593Smuzhiyun reg = <0x0 0x40000000 0 0x80000000>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun}; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun&A53_0 { 24*4882a593Smuzhiyun cpu-supply = <&buck2_reg>; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&ddrc { 28*4882a593Smuzhiyun operating-points-v2 = <&ddrc_opp_table>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun ddrc_opp_table: opp-table { 31*4882a593Smuzhiyun compatible = "operating-points-v2"; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun opp-25M { 34*4882a593Smuzhiyun opp-hz = /bits/ 64 <25000000>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun opp-100M { 38*4882a593Smuzhiyun opp-hz = /bits/ 64 <100000000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun opp-750M { 42*4882a593Smuzhiyun opp-hz = /bits/ 64 <750000000>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun}; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun&fec1 { 48*4882a593Smuzhiyun pinctrl-names = "default"; 49*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec1>; 50*4882a593Smuzhiyun phy-mode = "rgmii-id"; 51*4882a593Smuzhiyun phy-handle = <ðphy0>; 52*4882a593Smuzhiyun fsl,magic-packet; 53*4882a593Smuzhiyun status = "okay"; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun mdio { 56*4882a593Smuzhiyun #address-cells = <1>; 57*4882a593Smuzhiyun #size-cells = <0>; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 60*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 61*4882a593Smuzhiyun reg = <0>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun&i2c1 { 67*4882a593Smuzhiyun clock-frequency = <400000>; 68*4882a593Smuzhiyun pinctrl-names = "default"; 69*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 70*4882a593Smuzhiyun status = "okay"; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun pmic@4b { 73*4882a593Smuzhiyun compatible = "rohm,bd71847"; 74*4882a593Smuzhiyun reg = <0x4b>; 75*4882a593Smuzhiyun pinctrl-names = "default"; 76*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pmic>; 77*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 78*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 79*4882a593Smuzhiyun rohm,reset-snvs-powered; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun regulators { 82*4882a593Smuzhiyun buck1_reg: BUCK1 { 83*4882a593Smuzhiyun regulator-name = "buck1"; 84*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 85*4882a593Smuzhiyun regulator-max-microvolt = <1300000>; 86*4882a593Smuzhiyun regulator-boot-on; 87*4882a593Smuzhiyun regulator-always-on; 88*4882a593Smuzhiyun regulator-ramp-delay = <1250>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun buck2_reg: BUCK2 { 92*4882a593Smuzhiyun regulator-name = "buck2"; 93*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 94*4882a593Smuzhiyun regulator-max-microvolt = <1300000>; 95*4882a593Smuzhiyun regulator-boot-on; 96*4882a593Smuzhiyun regulator-always-on; 97*4882a593Smuzhiyun regulator-ramp-delay = <1250>; 98*4882a593Smuzhiyun rohm,dvs-run-voltage = <1000000>; 99*4882a593Smuzhiyun rohm,dvs-idle-voltage = <900000>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun buck3_reg: BUCK3 { 103*4882a593Smuzhiyun // BUCK5 in datasheet 104*4882a593Smuzhiyun regulator-name = "buck3"; 105*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 106*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 107*4882a593Smuzhiyun regulator-boot-on; 108*4882a593Smuzhiyun regulator-always-on; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun buck4_reg: BUCK4 { 112*4882a593Smuzhiyun // BUCK6 in datasheet 113*4882a593Smuzhiyun regulator-name = "buck4"; 114*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 115*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 116*4882a593Smuzhiyun regulator-boot-on; 117*4882a593Smuzhiyun regulator-always-on; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun buck5_reg: BUCK5 { 121*4882a593Smuzhiyun // BUCK7 in datasheet 122*4882a593Smuzhiyun regulator-name = "buck5"; 123*4882a593Smuzhiyun regulator-min-microvolt = <1605000>; 124*4882a593Smuzhiyun regulator-max-microvolt = <1995000>; 125*4882a593Smuzhiyun regulator-boot-on; 126*4882a593Smuzhiyun regulator-always-on; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun buck6_reg: BUCK6 { 130*4882a593Smuzhiyun // BUCK8 in datasheet 131*4882a593Smuzhiyun regulator-name = "buck6"; 132*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 133*4882a593Smuzhiyun regulator-max-microvolt = <1400000>; 134*4882a593Smuzhiyun regulator-boot-on; 135*4882a593Smuzhiyun regulator-always-on; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun ldo1_reg: LDO1 { 139*4882a593Smuzhiyun regulator-name = "ldo1"; 140*4882a593Smuzhiyun regulator-min-microvolt = <1600000>; 141*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 142*4882a593Smuzhiyun regulator-boot-on; 143*4882a593Smuzhiyun regulator-always-on; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun ldo2_reg: LDO2 { 147*4882a593Smuzhiyun regulator-name = "ldo2"; 148*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 149*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 150*4882a593Smuzhiyun regulator-boot-on; 151*4882a593Smuzhiyun regulator-always-on; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun ldo3_reg: LDO3 { 155*4882a593Smuzhiyun regulator-name = "ldo3"; 156*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 157*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 158*4882a593Smuzhiyun regulator-boot-on; 159*4882a593Smuzhiyun regulator-always-on; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun ldo4_reg: LDO4 { 163*4882a593Smuzhiyun regulator-name = "ldo4"; 164*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 165*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 166*4882a593Smuzhiyun regulator-boot-on; 167*4882a593Smuzhiyun regulator-always-on; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun ldo6_reg: LDO6 { 171*4882a593Smuzhiyun regulator-name = "ldo6"; 172*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 173*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 174*4882a593Smuzhiyun regulator-boot-on; 175*4882a593Smuzhiyun regulator-always-on; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun}; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun&i2c3 { 182*4882a593Smuzhiyun clock-frequency = <400000>; 183*4882a593Smuzhiyun pinctrl-names = "default"; 184*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 185*4882a593Smuzhiyun status = "okay"; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun eeprom@50 { 188*4882a593Smuzhiyun compatible = "microchip,24c64", "atmel,24c64"; 189*4882a593Smuzhiyun pagesize = <32>; 190*4882a593Smuzhiyun read-only; /* Manufacturing EEPROM programmed at factory */ 191*4882a593Smuzhiyun reg = <0x50>; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun rtc@51 { 195*4882a593Smuzhiyun compatible = "nxp,pcf85263"; 196*4882a593Smuzhiyun reg = <0x51>; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&uart1 { 201*4882a593Smuzhiyun pinctrl-names = "default"; 202*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 203*4882a593Smuzhiyun assigned-clocks = <&clk IMX8MM_CLK_UART1>; 204*4882a593Smuzhiyun assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 205*4882a593Smuzhiyun uart-has-rtscts; 206*4882a593Smuzhiyun status = "okay"; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun bluetooth { 209*4882a593Smuzhiyun compatible = "brcm,bcm43438-bt"; 210*4882a593Smuzhiyun shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 211*4882a593Smuzhiyun host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 212*4882a593Smuzhiyun device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 213*4882a593Smuzhiyun clocks = <&osc_32k>; 214*4882a593Smuzhiyun max-speed = <4000000>; 215*4882a593Smuzhiyun clock-names = "extclk"; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun}; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun&usdhc1 { 220*4882a593Smuzhiyun #address-cells = <1>; 221*4882a593Smuzhiyun #size-cells = <0>; 222*4882a593Smuzhiyun pinctrl-names = "default"; 223*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc1>; 224*4882a593Smuzhiyun bus-width = <4>; 225*4882a593Smuzhiyun non-removable; 226*4882a593Smuzhiyun cap-power-off-card; 227*4882a593Smuzhiyun pm-ignore-notify; 228*4882a593Smuzhiyun keep-power-in-suspend; 229*4882a593Smuzhiyun mmc-pwrseq = <&usdhc1_pwrseq>; 230*4882a593Smuzhiyun status = "okay"; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun brcmf: bcrmf@1 { 233*4882a593Smuzhiyun reg = <1>; 234*4882a593Smuzhiyun compatible = "brcm,bcm4329-fmac"; 235*4882a593Smuzhiyun pinctrl-names = "default"; 236*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wlan>; 237*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 238*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 239*4882a593Smuzhiyun interrupt-names = "host-wake"; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun}; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun&usdhc3 { 244*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 245*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 246*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 247*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 248*4882a593Smuzhiyun bus-width = <8>; 249*4882a593Smuzhiyun non-removable; 250*4882a593Smuzhiyun status = "okay"; 251*4882a593Smuzhiyun}; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun&wdog1 { 254*4882a593Smuzhiyun pinctrl-names = "default"; 255*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 256*4882a593Smuzhiyun fsl,ext-reset-output; 257*4882a593Smuzhiyun status = "okay"; 258*4882a593Smuzhiyun}; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun&iomuxc { 261*4882a593Smuzhiyun pinctrl_fec1: fec1grp { 262*4882a593Smuzhiyun fsl,pins = < 263*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 264*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 265*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 266*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 267*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 268*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 269*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 270*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 271*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 272*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 273*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 274*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 275*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 276*4882a593Smuzhiyun MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 277*4882a593Smuzhiyun MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 278*4882a593Smuzhiyun >; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 282*4882a593Smuzhiyun fsl,pins = < 283*4882a593Smuzhiyun MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 284*4882a593Smuzhiyun MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 285*4882a593Smuzhiyun >; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 289*4882a593Smuzhiyun fsl,pins = < 290*4882a593Smuzhiyun MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 291*4882a593Smuzhiyun MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 292*4882a593Smuzhiyun >; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun pinctrl_pmic: pmicirqgrp { 296*4882a593Smuzhiyun fsl,pins = < 297*4882a593Smuzhiyun MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 298*4882a593Smuzhiyun >; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 302*4882a593Smuzhiyun fsl,pins = < 303*4882a593Smuzhiyun MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 304*4882a593Smuzhiyun MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 305*4882a593Smuzhiyun MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 306*4882a593Smuzhiyun MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 307*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 308*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 309*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 310*4882a593Smuzhiyun MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 311*4882a593Smuzhiyun >; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun pinctrl_usdhc1_gpio: usdhc1gpiogrp { 315*4882a593Smuzhiyun fsl,pins = < 316*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 317*4882a593Smuzhiyun >; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun pinctrl_usdhc1: usdhc1grp { 321*4882a593Smuzhiyun fsl,pins = < 322*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 323*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 324*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 325*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 326*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 327*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 328*4882a593Smuzhiyun >; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 332*4882a593Smuzhiyun fsl,pins = < 333*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 334*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 335*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 336*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 337*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 338*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 339*4882a593Smuzhiyun >; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 343*4882a593Smuzhiyun fsl,pins = < 344*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 345*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 346*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 347*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 348*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 349*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 350*4882a593Smuzhiyun >; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 354*4882a593Smuzhiyun fsl,pins = < 355*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 356*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 357*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 358*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 359*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 360*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 361*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 362*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 363*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 364*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 365*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 366*4882a593Smuzhiyun >; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 370*4882a593Smuzhiyun fsl,pins = < 371*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 372*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 373*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 374*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 375*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 376*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 377*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 378*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 379*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 380*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 381*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 382*4882a593Smuzhiyun >; 383*4882a593Smuzhiyun }; 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 386*4882a593Smuzhiyun fsl,pins = < 387*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 388*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 389*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 390*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 391*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 392*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 393*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 394*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 395*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 396*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 397*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 398*4882a593Smuzhiyun >; 399*4882a593Smuzhiyun }; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 402*4882a593Smuzhiyun fsl,pins = < 403*4882a593Smuzhiyun MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 404*4882a593Smuzhiyun >; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun pinctrl_wlan: wlangrp { 408*4882a593Smuzhiyun fsl,pins = < 409*4882a593Smuzhiyun MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 410*4882a593Smuzhiyun >; 411*4882a593Smuzhiyun }; 412*4882a593Smuzhiyun}; 413