xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1088a-qds.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree file for NXP LS1088A QDS Board.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2017 NXP
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Harninder Rai <harninder.rai@nxp.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/dts-v1/;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun#include "fsl-ls1088a.dtsi"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun/ {
16*4882a593Smuzhiyun	model = "LS1088A QDS Board";
17*4882a593Smuzhiyun	compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
18*4882a593Smuzhiyun};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun&dspi {
21*4882a593Smuzhiyun	bus-num = <0>;
22*4882a593Smuzhiyun	status = "okay";
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	flash@0 {
25*4882a593Smuzhiyun		#address-cells = <1>;
26*4882a593Smuzhiyun		#size-cells = <1>;
27*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
28*4882a593Smuzhiyun		reg = <0>;
29*4882a593Smuzhiyun		spi-max-frequency = <1000000>;
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	flash@1 {
33*4882a593Smuzhiyun		#address-cells = <1>;
34*4882a593Smuzhiyun		#size-cells = <1>;
35*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
36*4882a593Smuzhiyun		spi-cpol;
37*4882a593Smuzhiyun		spi-cpha;
38*4882a593Smuzhiyun		spi-max-frequency = <3500000>;
39*4882a593Smuzhiyun		reg = <1>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	flash@2 {
43*4882a593Smuzhiyun		#address-cells = <1>;
44*4882a593Smuzhiyun		#size-cells = <1>;
45*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
46*4882a593Smuzhiyun		spi-cpol;
47*4882a593Smuzhiyun		spi-cpha;
48*4882a593Smuzhiyun		spi-max-frequency = <3500000>;
49*4882a593Smuzhiyun		reg = <2>;
50*4882a593Smuzhiyun	};
51*4882a593Smuzhiyun};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun&i2c0 {
54*4882a593Smuzhiyun	status = "okay";
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	i2c-switch@77 {
57*4882a593Smuzhiyun		compatible = "nxp,pca9547";
58*4882a593Smuzhiyun		reg = <0x77>;
59*4882a593Smuzhiyun		#address-cells = <1>;
60*4882a593Smuzhiyun		#size-cells = <0>;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		i2c@2 {
63*4882a593Smuzhiyun			#address-cells = <1>;
64*4882a593Smuzhiyun			#size-cells = <0>;
65*4882a593Smuzhiyun			reg = <0x2>;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun			ina220@40 {
68*4882a593Smuzhiyun				compatible = "ti,ina220";
69*4882a593Smuzhiyun				reg = <0x40>;
70*4882a593Smuzhiyun				shunt-resistor = <1000>;
71*4882a593Smuzhiyun			};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun			ina220@41 {
74*4882a593Smuzhiyun				compatible = "ti,ina220";
75*4882a593Smuzhiyun				reg = <0x41>;
76*4882a593Smuzhiyun				shunt-resistor = <1000>;
77*4882a593Smuzhiyun			};
78*4882a593Smuzhiyun		};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun		i2c@3 {
81*4882a593Smuzhiyun			#address-cells = <1>;
82*4882a593Smuzhiyun			#size-cells = <0>;
83*4882a593Smuzhiyun			reg = <0x3>;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun			temp-sensor@4c {
86*4882a593Smuzhiyun				compatible = "adi,adt7461a";
87*4882a593Smuzhiyun				reg = <0x4c>;
88*4882a593Smuzhiyun			};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun			rtc@51 {
91*4882a593Smuzhiyun				compatible = "nxp,pcf2129";
92*4882a593Smuzhiyun				reg = <0x51>;
93*4882a593Smuzhiyun				/* IRQ10_B */
94*4882a593Smuzhiyun				interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
95*4882a593Smuzhiyun			};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun			eeprom@56 {
98*4882a593Smuzhiyun				compatible = "atmel,24c512";
99*4882a593Smuzhiyun				reg = <0x56>;
100*4882a593Smuzhiyun			};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun			eeprom@57 {
103*4882a593Smuzhiyun				compatible = "atmel,24c512";
104*4882a593Smuzhiyun				reg = <0x57>;
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun		};
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun&ifc {
111*4882a593Smuzhiyun	ranges = <0 0 0x5 0x80000000 0x08000000
112*4882a593Smuzhiyun		  2 0 0x5 0x30000000 0x00010000
113*4882a593Smuzhiyun		  3 0 0x5 0x20000000 0x00010000>;
114*4882a593Smuzhiyun	status = "okay";
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun	nor@0,0 {
117*4882a593Smuzhiyun		compatible = "cfi-flash";
118*4882a593Smuzhiyun		reg = <0x0 0x0 0x8000000>;
119*4882a593Smuzhiyun		bank-width = <2>;
120*4882a593Smuzhiyun		device-width = <1>;
121*4882a593Smuzhiyun	};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun	nand@2,0 {
124*4882a593Smuzhiyun		compatible = "fsl,ifc-nand";
125*4882a593Smuzhiyun		reg = <0x2 0x0 0x10000>;
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	fpga: board-control@3,0 {
129*4882a593Smuzhiyun		compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
130*4882a593Smuzhiyun		reg = <0x3 0x0 0x0000100>;
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun&duart0 {
135*4882a593Smuzhiyun	status = "okay";
136*4882a593Smuzhiyun};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun&duart1 {
139*4882a593Smuzhiyun	status = "okay";
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&esdhc {
143*4882a593Smuzhiyun	status = "okay";
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&qspi {
147*4882a593Smuzhiyun	status = "okay";
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun	s25fs512s0: flash@0 {
150*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
151*4882a593Smuzhiyun		#address-cells = <1>;
152*4882a593Smuzhiyun		#size-cells = <1>;
153*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
154*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
155*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
156*4882a593Smuzhiyun		reg = <0>;
157*4882a593Smuzhiyun	};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun	s25fs512s1: flash@1 {
160*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
161*4882a593Smuzhiyun		#address-cells = <1>;
162*4882a593Smuzhiyun		#size-cells = <1>;
163*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
164*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
165*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
166*4882a593Smuzhiyun		reg = <1>;
167*4882a593Smuzhiyun	};
168*4882a593Smuzhiyun};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun&sata {
171*4882a593Smuzhiyun	status = "okay";
172*4882a593Smuzhiyun};
173