xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1046a-rdb.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Mingkai Hu <mingkai.hu@nxp.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/dts-v1/;
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun#include "fsl-ls1046a.dtsi"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	model = "LS1046A RDB Board";
16*4882a593Smuzhiyun	compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	aliases {
19*4882a593Smuzhiyun		serial0 = &duart0;
20*4882a593Smuzhiyun		serial1 = &duart1;
21*4882a593Smuzhiyun		serial2 = &duart2;
22*4882a593Smuzhiyun		serial3 = &duart3;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	chosen {
26*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun&duart0 {
31*4882a593Smuzhiyun	status = "okay";
32*4882a593Smuzhiyun};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun&duart1 {
35*4882a593Smuzhiyun	status = "okay";
36*4882a593Smuzhiyun};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun&esdhc {
39*4882a593Smuzhiyun	mmc-hs200-1_8v;
40*4882a593Smuzhiyun	sd-uhs-sdr104;
41*4882a593Smuzhiyun	sd-uhs-sdr50;
42*4882a593Smuzhiyun	sd-uhs-sdr25;
43*4882a593Smuzhiyun	sd-uhs-sdr12;
44*4882a593Smuzhiyun};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun&i2c0 {
47*4882a593Smuzhiyun	status = "okay";
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun	ina220@40 {
50*4882a593Smuzhiyun		compatible = "ti,ina220";
51*4882a593Smuzhiyun		reg = <0x40>;
52*4882a593Smuzhiyun		shunt-resistor = <1000>;
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	temp-sensor@4c {
56*4882a593Smuzhiyun		compatible = "adi,adt7461";
57*4882a593Smuzhiyun		reg = <0x4c>;
58*4882a593Smuzhiyun	};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun	eeprom@52 {
61*4882a593Smuzhiyun		compatible = "onnn,cat24c05", "atmel,24c04";
62*4882a593Smuzhiyun		reg = <0x52>;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun&i2c3 {
67*4882a593Smuzhiyun	status = "okay";
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	rtc@51 {
70*4882a593Smuzhiyun		compatible = "nxp,pcf2129";
71*4882a593Smuzhiyun		reg = <0x51>;
72*4882a593Smuzhiyun	};
73*4882a593Smuzhiyun};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun&ifc {
76*4882a593Smuzhiyun	#address-cells = <2>;
77*4882a593Smuzhiyun	#size-cells = <1>;
78*4882a593Smuzhiyun	/* NAND Flashe and CPLD on board */
79*4882a593Smuzhiyun	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
80*4882a593Smuzhiyun		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
81*4882a593Smuzhiyun	status = "okay";
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	nand@0,0 {
84*4882a593Smuzhiyun		compatible = "fsl,ifc-nand";
85*4882a593Smuzhiyun		#address-cells = <1>;
86*4882a593Smuzhiyun		#size-cells = <1>;
87*4882a593Smuzhiyun		reg = <0x0 0x0 0x10000>;
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	cpld: board-control@2,0 {
91*4882a593Smuzhiyun		compatible = "fsl,ls1046ardb-cpld";
92*4882a593Smuzhiyun		reg = <0x2 0x0 0x0000100>;
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun&qspi {
97*4882a593Smuzhiyun	status = "okay";
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	s25fs512s0: flash@0 {
100*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
101*4882a593Smuzhiyun		#address-cells = <1>;
102*4882a593Smuzhiyun		#size-cells = <1>;
103*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
104*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
105*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
106*4882a593Smuzhiyun		reg = <0>;
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun	s25fs512s1: flash@1 {
110*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
111*4882a593Smuzhiyun		#address-cells = <1>;
112*4882a593Smuzhiyun		#size-cells = <1>;
113*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
114*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
115*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
116*4882a593Smuzhiyun		reg = <1>;
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun&usb1 {
121*4882a593Smuzhiyun	dr_mode = "otg";
122*4882a593Smuzhiyun};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun#include "fsl-ls1046-post.dtsi"
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun&fman0 {
127*4882a593Smuzhiyun	ethernet@e4000 {
128*4882a593Smuzhiyun		phy-handle = <&rgmii_phy1>;
129*4882a593Smuzhiyun		phy-connection-type = "rgmii-id";
130*4882a593Smuzhiyun	};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun	ethernet@e6000 {
133*4882a593Smuzhiyun		phy-handle = <&rgmii_phy2>;
134*4882a593Smuzhiyun		phy-connection-type = "rgmii-id";
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	ethernet@e8000 {
138*4882a593Smuzhiyun		phy-handle = <&sgmii_phy1>;
139*4882a593Smuzhiyun		phy-connection-type = "sgmii";
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	ethernet@ea000 {
143*4882a593Smuzhiyun		phy-handle = <&sgmii_phy2>;
144*4882a593Smuzhiyun		phy-connection-type = "sgmii";
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun	ethernet@f0000 { /* 10GEC1 */
148*4882a593Smuzhiyun		phy-handle = <&aqr106_phy>;
149*4882a593Smuzhiyun		phy-connection-type = "xgmii";
150*4882a593Smuzhiyun	};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun	ethernet@f2000 { /* 10GEC2 */
153*4882a593Smuzhiyun		fixed-link = <0 1 1000 0 0>;
154*4882a593Smuzhiyun		phy-connection-type = "xgmii";
155*4882a593Smuzhiyun	};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun	mdio@fc000 {
158*4882a593Smuzhiyun		rgmii_phy1: ethernet-phy@1 {
159*4882a593Smuzhiyun			reg = <0x1>;
160*4882a593Smuzhiyun		};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun		rgmii_phy2: ethernet-phy@2 {
163*4882a593Smuzhiyun			reg = <0x2>;
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun		sgmii_phy1: ethernet-phy@3 {
167*4882a593Smuzhiyun			reg = <0x3>;
168*4882a593Smuzhiyun		};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun		sgmii_phy2: ethernet-phy@4 {
171*4882a593Smuzhiyun			reg = <0x4>;
172*4882a593Smuzhiyun		};
173*4882a593Smuzhiyun	};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun	mdio@fd000 {
176*4882a593Smuzhiyun		aqr106_phy: ethernet-phy@0 {
177*4882a593Smuzhiyun			compatible = "ethernet-phy-ieee802.3-c45";
178*4882a593Smuzhiyun			interrupts = <0 131 4>;
179*4882a593Smuzhiyun			reg = <0x0>;
180*4882a593Smuzhiyun		};
181*4882a593Smuzhiyun	};
182*4882a593Smuzhiyun};
183