1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for the Kontron SMARC-sAL28 board. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2019 Michael Walle <michael@walle.cc> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun#include "fsl-ls1028a.dtsi" 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 13*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "Kontron SMARC-sAL28"; 17*4882a593Smuzhiyun compatible = "kontron,sl28", "fsl,ls1028a"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun aliases { 20*4882a593Smuzhiyun crypto = &crypto; 21*4882a593Smuzhiyun serial0 = &duart0; 22*4882a593Smuzhiyun serial1 = &duart1; 23*4882a593Smuzhiyun serial2 = &lpuart1; 24*4882a593Smuzhiyun spi0 = &fspi; 25*4882a593Smuzhiyun spi1 = &dspi2; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun buttons0 { 29*4882a593Smuzhiyun compatible = "gpio-keys"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun power-button { 32*4882a593Smuzhiyun interrupts-extended = <&sl28cpld_intc 33*4882a593Smuzhiyun 4 IRQ_TYPE_EDGE_BOTH>; 34*4882a593Smuzhiyun linux,code = <KEY_POWER>; 35*4882a593Smuzhiyun label = "Power"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun sleep-button { 39*4882a593Smuzhiyun interrupts-extended = <&sl28cpld_intc 40*4882a593Smuzhiyun 5 IRQ_TYPE_EDGE_BOTH>; 41*4882a593Smuzhiyun linux,code = <KEY_SLEEP>; 42*4882a593Smuzhiyun label = "Sleep"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun buttons1 { 47*4882a593Smuzhiyun compatible = "gpio-keys-polled"; 48*4882a593Smuzhiyun poll-interval = <200>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun lid-switch { 51*4882a593Smuzhiyun linux,input-type = <EV_SW>; 52*4882a593Smuzhiyun linux,code = <SW_LID>; 53*4882a593Smuzhiyun gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>; 54*4882a593Smuzhiyun label = "Lid"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun chosen { 59*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun&dspi2 { 64*4882a593Smuzhiyun status = "okay"; 65*4882a593Smuzhiyun}; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun&duart0 { 68*4882a593Smuzhiyun status = "okay"; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&duart1 { 72*4882a593Smuzhiyun status = "okay"; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&enetc_port0 { 76*4882a593Smuzhiyun phy-handle = <&phy0>; 77*4882a593Smuzhiyun phy-connection-type = "sgmii"; 78*4882a593Smuzhiyun managed = "in-band-status"; 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun mdio { 82*4882a593Smuzhiyun #address-cells = <1>; 83*4882a593Smuzhiyun #size-cells = <0>; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun phy0: ethernet-phy@5 { 86*4882a593Smuzhiyun reg = <0x5>; 87*4882a593Smuzhiyun eee-broken-1000t; 88*4882a593Smuzhiyun eee-broken-100tx; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&esdhc { 94*4882a593Smuzhiyun sd-uhs-sdr104; 95*4882a593Smuzhiyun sd-uhs-sdr50; 96*4882a593Smuzhiyun sd-uhs-sdr25; 97*4882a593Smuzhiyun sd-uhs-sdr12; 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&esdhc1 { 102*4882a593Smuzhiyun mmc-hs200-1_8v; 103*4882a593Smuzhiyun mmc-hs400-1_8v; 104*4882a593Smuzhiyun bus-width = <8>; 105*4882a593Smuzhiyun status = "okay"; 106*4882a593Smuzhiyun}; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun&fspi { 109*4882a593Smuzhiyun status = "okay"; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun flash@0 { 112*4882a593Smuzhiyun #address-cells = <1>; 113*4882a593Smuzhiyun #size-cells = <1>; 114*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 115*4882a593Smuzhiyun m25p,fast-read; 116*4882a593Smuzhiyun spi-max-frequency = <133000000>; 117*4882a593Smuzhiyun reg = <0>; 118*4882a593Smuzhiyun /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */ 119*4882a593Smuzhiyun spi-rx-bus-width = <2>; /* 2 SPI Rx lines */ 120*4882a593Smuzhiyun spi-tx-bus-width = <1>; /* 1 SPI Tx line */ 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun partition@0 { 123*4882a593Smuzhiyun reg = <0x000000 0x010000>; 124*4882a593Smuzhiyun label = "rcw"; 125*4882a593Smuzhiyun read-only; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun partition@10000 { 129*4882a593Smuzhiyun reg = <0x010000 0x0f0000>; 130*4882a593Smuzhiyun label = "failsafe bootloader"; 131*4882a593Smuzhiyun read-only; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun partition@100000 { 135*4882a593Smuzhiyun reg = <0x100000 0x040000>; 136*4882a593Smuzhiyun label = "failsafe DP firmware"; 137*4882a593Smuzhiyun read-only; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun partition@140000 { 141*4882a593Smuzhiyun reg = <0x140000 0x0a0000>; 142*4882a593Smuzhiyun label = "failsafe trusted firmware"; 143*4882a593Smuzhiyun read-only; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun partition@1e0000 { 147*4882a593Smuzhiyun reg = <0x1e0000 0x020000>; 148*4882a593Smuzhiyun label = "reserved"; 149*4882a593Smuzhiyun read-only; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun partition@200000 { 153*4882a593Smuzhiyun reg = <0x200000 0x010000>; 154*4882a593Smuzhiyun label = "configuration store"; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun partition@210000 { 158*4882a593Smuzhiyun reg = <0x210000 0x1d0000>; 159*4882a593Smuzhiyun label = "bootloader"; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun partition@3e0000 { 163*4882a593Smuzhiyun reg = <0x3e0000 0x020000>; 164*4882a593Smuzhiyun label = "bootloader environment"; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun}; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun&gpio1 { 170*4882a593Smuzhiyun gpio-line-names = 171*4882a593Smuzhiyun "", "", "", "", "", "", "", "", 172*4882a593Smuzhiyun "", "", "", "", "", "", "", "", 173*4882a593Smuzhiyun "", "", "", "", "", "", "TDO", "TCK", 174*4882a593Smuzhiyun "", "", "", "", "", "", "", ""; 175*4882a593Smuzhiyun}; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun&gpio2 { 178*4882a593Smuzhiyun gpio-line-names = 179*4882a593Smuzhiyun "", "", "", "", "", "", "TMS", "TDI", 180*4882a593Smuzhiyun "", "", "", "", "", "", "", "", 181*4882a593Smuzhiyun "", "", "", "", "", "", "", "", 182*4882a593Smuzhiyun "", "", "", "", "", "", "", ""; 183*4882a593Smuzhiyun}; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun&i2c0 { 186*4882a593Smuzhiyun status = "okay"; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun rtc@32 { 189*4882a593Smuzhiyun compatible = "microcrystal,rv8803"; 190*4882a593Smuzhiyun reg = <0x32>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun sl28cpld@4a { 194*4882a593Smuzhiyun compatible = "kontron,sl28cpld"; 195*4882a593Smuzhiyun reg = <0x4a>; 196*4882a593Smuzhiyun #address-cells = <1>; 197*4882a593Smuzhiyun #size-cells = <0>; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun watchdog@4 { 200*4882a593Smuzhiyun compatible = "kontron,sl28cpld-wdt"; 201*4882a593Smuzhiyun reg = <0x4>; 202*4882a593Smuzhiyun kontron,assert-wdt-timeout-pin; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun hwmon@b { 206*4882a593Smuzhiyun compatible = "kontron,sl28cpld-fan"; 207*4882a593Smuzhiyun reg = <0xb>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun sl28cpld_pwm0: pwm@c { 211*4882a593Smuzhiyun compatible = "kontron,sl28cpld-pwm"; 212*4882a593Smuzhiyun reg = <0xc>; 213*4882a593Smuzhiyun #pwm-cells = <2>; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun sl28cpld_pwm1: pwm@e { 217*4882a593Smuzhiyun compatible = "kontron,sl28cpld-pwm"; 218*4882a593Smuzhiyun reg = <0xe>; 219*4882a593Smuzhiyun #pwm-cells = <2>; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun sl28cpld_gpio0: gpio@10 { 223*4882a593Smuzhiyun compatible = "kontron,sl28cpld-gpio"; 224*4882a593Smuzhiyun reg = <0x10>; 225*4882a593Smuzhiyun interrupts-extended = <&gpio2 6 226*4882a593Smuzhiyun IRQ_TYPE_EDGE_FALLING>; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun gpio-controller; 229*4882a593Smuzhiyun #gpio-cells = <2>; 230*4882a593Smuzhiyun gpio-line-names = 231*4882a593Smuzhiyun "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N", 232*4882a593Smuzhiyun "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N", 233*4882a593Smuzhiyun "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT", 234*4882a593Smuzhiyun "GPIO6_TACHIN", "GPIO7"; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun interrupt-controller; 237*4882a593Smuzhiyun #interrupt-cells = <2>; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun sl28cpld_gpio1: gpio@15 { 241*4882a593Smuzhiyun compatible = "kontron,sl28cpld-gpio"; 242*4882a593Smuzhiyun reg = <0x15>; 243*4882a593Smuzhiyun interrupts-extended = <&gpio2 6 244*4882a593Smuzhiyun IRQ_TYPE_EDGE_FALLING>; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun gpio-controller; 247*4882a593Smuzhiyun #gpio-cells = <2>; 248*4882a593Smuzhiyun gpio-line-names = 249*4882a593Smuzhiyun "GPIO8", "GPIO9", "GPIO10", "GPIO11", 250*4882a593Smuzhiyun "", "", "", ""; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun interrupt-controller; 253*4882a593Smuzhiyun #interrupt-cells = <2>; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun sl28cpld_gpio2: gpio@1a { 257*4882a593Smuzhiyun compatible = "kontron,sl28cpld-gpo"; 258*4882a593Smuzhiyun reg = <0x1a>; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun gpio-controller; 261*4882a593Smuzhiyun #gpio-cells = <2>; 262*4882a593Smuzhiyun gpio-line-names = 263*4882a593Smuzhiyun "LCD0 voltage enable", 264*4882a593Smuzhiyun "LCD0 backlight enable", 265*4882a593Smuzhiyun "eMMC reset", "LVDS bridge reset", 266*4882a593Smuzhiyun "LVDS bridge power-down", 267*4882a593Smuzhiyun "SDIO power enable", 268*4882a593Smuzhiyun "", ""; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun sl28cpld_gpio3: gpio@1b { 272*4882a593Smuzhiyun compatible = "kontron,sl28cpld-gpi"; 273*4882a593Smuzhiyun reg = <0x1b>; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun gpio-controller; 276*4882a593Smuzhiyun #gpio-cells = <2>; 277*4882a593Smuzhiyun gpio-line-names = 278*4882a593Smuzhiyun "Power button", "Force recovery", "Sleep", 279*4882a593Smuzhiyun "Battery low", "Lid state", "Charging", 280*4882a593Smuzhiyun "Charger present", ""; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun sl28cpld_intc: interrupt-controller@1c { 284*4882a593Smuzhiyun compatible = "kontron,sl28cpld-intc"; 285*4882a593Smuzhiyun reg = <0x1c>; 286*4882a593Smuzhiyun interrupts-extended = <&gpio2 6 287*4882a593Smuzhiyun IRQ_TYPE_EDGE_FALLING>; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun interrupt-controller; 290*4882a593Smuzhiyun #interrupt-cells = <2>; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun eeprom@50 { 295*4882a593Smuzhiyun compatible = "atmel,24c32"; 296*4882a593Smuzhiyun reg = <0x50>; 297*4882a593Smuzhiyun pagesize = <32>; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun}; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun&i2c3 { 302*4882a593Smuzhiyun status = "okay"; 303*4882a593Smuzhiyun}; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun&i2c4 { 306*4882a593Smuzhiyun status = "okay"; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun eeprom@50 { 309*4882a593Smuzhiyun compatible = "atmel,24c32"; 310*4882a593Smuzhiyun reg = <0x50>; 311*4882a593Smuzhiyun pagesize = <32>; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun}; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun&lpuart1 { 316*4882a593Smuzhiyun status = "okay"; 317*4882a593Smuzhiyun}; 318