1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2017 BayLibre SAS 4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun gpu_opp_table: opp-table { 9*4882a593Smuzhiyun compatible = "operating-points-v2"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun opp-125000000 { 12*4882a593Smuzhiyun opp-hz = /bits/ 64 <125000000>; 13*4882a593Smuzhiyun opp-microvolt = <950000>; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun opp-250000000 { 16*4882a593Smuzhiyun opp-hz = /bits/ 64 <250000000>; 17*4882a593Smuzhiyun opp-microvolt = <950000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun opp-285714285 { 20*4882a593Smuzhiyun opp-hz = /bits/ 64 <285714285>; 21*4882a593Smuzhiyun opp-microvolt = <950000>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun opp-400000000 { 24*4882a593Smuzhiyun opp-hz = /bits/ 64 <400000000>; 25*4882a593Smuzhiyun opp-microvolt = <950000>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun opp-500000000 { 28*4882a593Smuzhiyun opp-hz = /bits/ 64 <500000000>; 29*4882a593Smuzhiyun opp-microvolt = <950000>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun opp-666666666 { 32*4882a593Smuzhiyun opp-hz = /bits/ 64 <666666666>; 33*4882a593Smuzhiyun opp-microvolt = <950000>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun opp-744000000 { 36*4882a593Smuzhiyun opp-hz = /bits/ 64 <744000000>; 37*4882a593Smuzhiyun opp-microvolt = <950000>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&apb { 43*4882a593Smuzhiyun mali: gpu@c0000 { 44*4882a593Smuzhiyun compatible = "arm,mali-450"; 45*4882a593Smuzhiyun reg = <0x0 0xc0000 0x0 0x40000>; 46*4882a593Smuzhiyun interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 47*4882a593Smuzhiyun <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 48*4882a593Smuzhiyun <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 49*4882a593Smuzhiyun <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 50*4882a593Smuzhiyun <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 51*4882a593Smuzhiyun <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 52*4882a593Smuzhiyun <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 53*4882a593Smuzhiyun <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 54*4882a593Smuzhiyun <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 55*4882a593Smuzhiyun <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 56*4882a593Smuzhiyun interrupt-names = "gp", "gpmmu", "pp", "pmu", 57*4882a593Smuzhiyun "pp0", "ppmmu0", "pp1", "ppmmu1", 58*4882a593Smuzhiyun "pp2", "ppmmu2"; 59*4882a593Smuzhiyun operating-points-v2 = <&gpu_opp_table>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62