1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/* 4*4882a593Smuzhiyun * Device tree file for ZII's SPB4 board 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPB - Seat Power Box 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2019 Zodiac Inflight Innovations 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun#include "vf610.dtsi" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "ZII VF610 SPB4 Board"; 16*4882a593Smuzhiyun compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun chosen { 19*4882a593Smuzhiyun stdout-path = &uart0; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun memory@80000000 { 23*4882a593Smuzhiyun device_type = "memory"; 24*4882a593Smuzhiyun reg = <0x80000000 0x20000000>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun gpio-leds { 28*4882a593Smuzhiyun compatible = "gpio-leds"; 29*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_leds_debug>; 30*4882a593Smuzhiyun pinctrl-names = "default"; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun led-debug { 33*4882a593Smuzhiyun label = "zii:green:debug1"; 34*4882a593Smuzhiyun gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; 35*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { 40*4882a593Smuzhiyun compatible = "regulator-fixed"; 41*4882a593Smuzhiyun regulator-name = "vcc_3v3_mcu"; 42*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 43*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun supply-voltage-monitor { 47*4882a593Smuzhiyun compatible = "iio-hwmon"; 48*4882a593Smuzhiyun io-channels = <&adc0 8>, /* 28V_SW */ 49*4882a593Smuzhiyun <&adc0 9>, /* +3.3V */ 50*4882a593Smuzhiyun <&adc1 8>, /* VCC_1V5 */ 51*4882a593Smuzhiyun <&adc1 9>; /* VCC_1V2 */ 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun&adc0 { 56*4882a593Smuzhiyun vref-supply = <®_vcc_3v3_mcu>; 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun}; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun&adc1 { 61*4882a593Smuzhiyun vref-supply = <®_vcc_3v3_mcu>; 62*4882a593Smuzhiyun status = "okay"; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&dspi1 { 66*4882a593Smuzhiyun bus-num = <1>; 67*4882a593Smuzhiyun pinctrl-names = "default"; 68*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_dspi1>; 69*4882a593Smuzhiyun status = "okay"; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun flash@0 { 72*4882a593Smuzhiyun #address-cells = <1>; 73*4882a593Smuzhiyun #size-cells = <1>; 74*4882a593Smuzhiyun compatible = "m25p128", "jedec,spi-nor"; 75*4882a593Smuzhiyun reg = <0>; 76*4882a593Smuzhiyun spi-max-frequency = <50000000>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&edma0 { 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&edma1 { 85*4882a593Smuzhiyun status = "okay"; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&esdhc0 { 89*4882a593Smuzhiyun pinctrl-names = "default"; 90*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc0>; 91*4882a593Smuzhiyun bus-width = <8>; 92*4882a593Smuzhiyun non-removable; 93*4882a593Smuzhiyun no-1-8-v; 94*4882a593Smuzhiyun keep-power-in-suspend; 95*4882a593Smuzhiyun no-sdio; 96*4882a593Smuzhiyun no-sd; 97*4882a593Smuzhiyun status = "okay"; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&esdhc1 { 101*4882a593Smuzhiyun pinctrl-names = "default"; 102*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 103*4882a593Smuzhiyun bus-width = <4>; 104*4882a593Smuzhiyun no-sdio; 105*4882a593Smuzhiyun status = "okay"; 106*4882a593Smuzhiyun}; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun&fec1 { 109*4882a593Smuzhiyun phy-mode = "rmii"; 110*4882a593Smuzhiyun pinctrl-names = "default"; 111*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec1>; 112*4882a593Smuzhiyun status = "okay"; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun fixed-link { 115*4882a593Smuzhiyun speed = <100>; 116*4882a593Smuzhiyun full-duplex; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun mdio1: mdio { 120*4882a593Smuzhiyun #address-cells = <1>; 121*4882a593Smuzhiyun #size-cells = <0>; 122*4882a593Smuzhiyun clock-frequency = <12500000>; 123*4882a593Smuzhiyun suppress-preamble; 124*4882a593Smuzhiyun status = "okay"; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun switch0: switch0@0 { 127*4882a593Smuzhiyun compatible = "marvell,mv88e6190"; 128*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_switch0>; 129*4882a593Smuzhiyun pinctrl-names = "default"; 130*4882a593Smuzhiyun reg = <0>; 131*4882a593Smuzhiyun eeprom-length = <65536>; 132*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 133*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 134*4882a593Smuzhiyun interrupt-controller; 135*4882a593Smuzhiyun #interrupt-cells = <2>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun ports { 138*4882a593Smuzhiyun #address-cells = <1>; 139*4882a593Smuzhiyun #size-cells = <0>; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun port@0 { 142*4882a593Smuzhiyun reg = <0>; 143*4882a593Smuzhiyun label = "cpu"; 144*4882a593Smuzhiyun ethernet = <&fec1>; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun fixed-link { 147*4882a593Smuzhiyun speed = <100>; 148*4882a593Smuzhiyun full-duplex; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun port@1 { 153*4882a593Smuzhiyun reg = <1>; 154*4882a593Smuzhiyun label = "eth_cu_1000_1"; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun port@2 { 158*4882a593Smuzhiyun reg = <2>; 159*4882a593Smuzhiyun label = "eth_cu_1000_2"; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun port@3 { 163*4882a593Smuzhiyun reg = <3>; 164*4882a593Smuzhiyun label = "eth_cu_1000_3"; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun port@4 { 168*4882a593Smuzhiyun reg = <4>; 169*4882a593Smuzhiyun label = "eth_cu_1000_4"; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun port@5 { 173*4882a593Smuzhiyun reg = <5>; 174*4882a593Smuzhiyun label = "eth_cu_1000_5"; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun port@6 { 178*4882a593Smuzhiyun reg = <6>; 179*4882a593Smuzhiyun label = "eth_cu_1000_6"; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun}; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun&i2c0 { 187*4882a593Smuzhiyun clock-frequency = <100000>; 188*4882a593Smuzhiyun pinctrl-names = "default"; 189*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c0>; 190*4882a593Smuzhiyun status = "okay"; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun io-expander@22 { 193*4882a593Smuzhiyun compatible = "nxp,pca9554"; 194*4882a593Smuzhiyun reg = <0x22>; 195*4882a593Smuzhiyun gpio-controller; 196*4882a593Smuzhiyun #gpio-cells = <2>; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun eeprom@50 { 200*4882a593Smuzhiyun compatible = "atmel,24c04"; 201*4882a593Smuzhiyun reg = <0x50>; 202*4882a593Smuzhiyun label = "nameplate"; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun eeprom@52 { 206*4882a593Smuzhiyun compatible = "atmel,24c04"; 207*4882a593Smuzhiyun reg = <0x52>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun}; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun&i2c1 { 212*4882a593Smuzhiyun clock-frequency = <100000>; 213*4882a593Smuzhiyun pinctrl-names = "default"; 214*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 215*4882a593Smuzhiyun status = "okay"; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun watchdog@38 { 218*4882a593Smuzhiyun compatible = "zii,rave-wdt"; 219*4882a593Smuzhiyun reg = <0x38>; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun}; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun&snvsrtc { 224*4882a593Smuzhiyun status = "disabled"; 225*4882a593Smuzhiyun}; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun&uart0 { 228*4882a593Smuzhiyun pinctrl-names = "default"; 229*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart0>; 230*4882a593Smuzhiyun status = "okay"; 231*4882a593Smuzhiyun}; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun&uart1 { 234*4882a593Smuzhiyun pinctrl-names = "default"; 235*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 236*4882a593Smuzhiyun status = "okay"; 237*4882a593Smuzhiyun}; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun&uart2 { 240*4882a593Smuzhiyun pinctrl-names = "default"; 241*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 242*4882a593Smuzhiyun status = "okay"; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun rave-sp { 245*4882a593Smuzhiyun compatible = "zii,rave-sp-rdu2"; 246*4882a593Smuzhiyun current-speed = <1000000>; 247*4882a593Smuzhiyun #address-cells = <1>; 248*4882a593Smuzhiyun #size-cells = <1>; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun watchdog { 251*4882a593Smuzhiyun compatible = "zii,rave-sp-watchdog"; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun eeprom@a3 { 255*4882a593Smuzhiyun compatible = "zii,rave-sp-eeprom"; 256*4882a593Smuzhiyun reg = <0xa3 0x4000>; 257*4882a593Smuzhiyun #address-cells = <1>; 258*4882a593Smuzhiyun #size-cells = <1>; 259*4882a593Smuzhiyun zii,eeprom-name = "main-eeprom"; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun}; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun&uart3 { 265*4882a593Smuzhiyun pinctrl-names = "default"; 266*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 267*4882a593Smuzhiyun status = "okay"; 268*4882a593Smuzhiyun}; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun&wdoga5 { 271*4882a593Smuzhiyun status = "disabled"; 272*4882a593Smuzhiyun}; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&iomuxc { 275*4882a593Smuzhiyun pinctrl_dspi1: dspi1grp { 276*4882a593Smuzhiyun fsl,pins = < 277*4882a593Smuzhiyun VF610_PAD_PTD5__DSPI1_CS0 0x1182 278*4882a593Smuzhiyun VF610_PAD_PTD4__DSPI1_CS1 0x1182 279*4882a593Smuzhiyun VF610_PAD_PTC6__DSPI1_SIN 0x1181 280*4882a593Smuzhiyun VF610_PAD_PTC7__DSPI1_SOUT 0x1182 281*4882a593Smuzhiyun VF610_PAD_PTC8__DSPI1_SCK 0x1182 282*4882a593Smuzhiyun >; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun pinctrl_esdhc0: esdhc0grp { 286*4882a593Smuzhiyun fsl,pins = < 287*4882a593Smuzhiyun VF610_PAD_PTC0__ESDHC0_CLK 0x31ef 288*4882a593Smuzhiyun VF610_PAD_PTC1__ESDHC0_CMD 0x31ef 289*4882a593Smuzhiyun VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef 290*4882a593Smuzhiyun VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef 291*4882a593Smuzhiyun VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef 292*4882a593Smuzhiyun VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef 293*4882a593Smuzhiyun VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef 294*4882a593Smuzhiyun VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef 295*4882a593Smuzhiyun VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef 296*4882a593Smuzhiyun VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef 297*4882a593Smuzhiyun >; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 301*4882a593Smuzhiyun fsl,pins = < 302*4882a593Smuzhiyun VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 303*4882a593Smuzhiyun VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 304*4882a593Smuzhiyun VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 305*4882a593Smuzhiyun VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef 306*4882a593Smuzhiyun VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef 307*4882a593Smuzhiyun VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef 308*4882a593Smuzhiyun >; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun pinctrl_fec1: fec1grp { 312*4882a593Smuzhiyun fsl,pins = < 313*4882a593Smuzhiyun VF610_PAD_PTA6__RMII_CLKIN 0x30d1 314*4882a593Smuzhiyun VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 315*4882a593Smuzhiyun VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 316*4882a593Smuzhiyun VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 317*4882a593Smuzhiyun VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 318*4882a593Smuzhiyun VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 319*4882a593Smuzhiyun VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 320*4882a593Smuzhiyun VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 321*4882a593Smuzhiyun VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 322*4882a593Smuzhiyun VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 323*4882a593Smuzhiyun >; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun pinctrl_gpio_switch0: pinctrl-gpio-switch0 { 327*4882a593Smuzhiyun fsl,pins = < 328*4882a593Smuzhiyun VF610_PAD_PTB28__GPIO_98 0x219d 329*4882a593Smuzhiyun >; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun pinctrl_i2c0: i2c0grp { 333*4882a593Smuzhiyun fsl,pins = < 334*4882a593Smuzhiyun VF610_PAD_PTB14__I2C0_SCL 0x37ff 335*4882a593Smuzhiyun VF610_PAD_PTB15__I2C0_SDA 0x37ff 336*4882a593Smuzhiyun >; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 340*4882a593Smuzhiyun fsl,pins = < 341*4882a593Smuzhiyun VF610_PAD_PTB16__I2C1_SCL 0x37ff 342*4882a593Smuzhiyun VF610_PAD_PTB17__I2C1_SDA 0x37ff 343*4882a593Smuzhiyun >; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun pinctrl_leds_debug: pinctrl-leds-debug { 347*4882a593Smuzhiyun fsl,pins = < 348*4882a593Smuzhiyun VF610_PAD_PTD3__GPIO_82 0x31c2 349*4882a593Smuzhiyun >; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun pinctrl_uart0: uart0grp { 353*4882a593Smuzhiyun fsl,pins = < 354*4882a593Smuzhiyun VF610_PAD_PTB10__UART0_TX 0x21a2 355*4882a593Smuzhiyun VF610_PAD_PTB11__UART0_RX 0x21a1 356*4882a593Smuzhiyun >; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 360*4882a593Smuzhiyun fsl,pins = < 361*4882a593Smuzhiyun VF610_PAD_PTB23__UART1_TX 0x21a2 362*4882a593Smuzhiyun VF610_PAD_PTB24__UART1_RX 0x21a1 363*4882a593Smuzhiyun >; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 367*4882a593Smuzhiyun fsl,pins = < 368*4882a593Smuzhiyun VF610_PAD_PTD0__UART2_TX 0x21a2 369*4882a593Smuzhiyun VF610_PAD_PTD1__UART2_RX 0x21a1 370*4882a593Smuzhiyun >; 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 374*4882a593Smuzhiyun fsl,pins = < 375*4882a593Smuzhiyun VF610_PAD_PTA30__UART3_TX 0x21a2 376*4882a593Smuzhiyun VF610_PAD_PTA31__UART3_RX 0x21a1 377*4882a593Smuzhiyun >; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun}; 380