1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2013 Linaro Limited 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include "vf610.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "PHYTEC Cosmic/Cosmic+ Board"; 12*4882a593Smuzhiyun compatible = "phytec,vf610-cosmic", "fsl,vf610"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun chosen { 15*4882a593Smuzhiyun bootargs = "console=ttyLP1,115200"; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun memory@80000000 { 19*4882a593Smuzhiyun device_type = "memory"; 20*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun enet_ext: enet_ext { 24*4882a593Smuzhiyun compatible = "fixed-clock"; 25*4882a593Smuzhiyun #clock-cells = <0>; 26*4882a593Smuzhiyun clock-frequency = <50000000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&clks { 31*4882a593Smuzhiyun clocks = <&sxosc>, <&fxosc>, <&enet_ext>; 32*4882a593Smuzhiyun clock-names = "sxosc", "fxosc", "enet_ext"; 33*4882a593Smuzhiyun}; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun&esdhc1 { 36*4882a593Smuzhiyun pinctrl-names = "default"; 37*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esdhc1>; 38*4882a593Smuzhiyun bus-width = <4>; 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&fec1 { 43*4882a593Smuzhiyun phy-mode = "rmii"; 44*4882a593Smuzhiyun pinctrl-names = "default"; 45*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec1>; 46*4882a593Smuzhiyun status = "okay"; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&iomuxc { 50*4882a593Smuzhiyun vf610-cosmic { 51*4882a593Smuzhiyun pinctrl_esdhc1: esdhc1grp { 52*4882a593Smuzhiyun fsl,pins = < 53*4882a593Smuzhiyun VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 54*4882a593Smuzhiyun VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 55*4882a593Smuzhiyun VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 56*4882a593Smuzhiyun VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef 57*4882a593Smuzhiyun VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef 58*4882a593Smuzhiyun VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef 59*4882a593Smuzhiyun VF610_PAD_PTB28__GPIO_98 0x219d 60*4882a593Smuzhiyun >; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun pinctrl_fec1: fec1grp { 64*4882a593Smuzhiyun fsl,pins = < 65*4882a593Smuzhiyun VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 66*4882a593Smuzhiyun VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 67*4882a593Smuzhiyun VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 68*4882a593Smuzhiyun VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 69*4882a593Smuzhiyun VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 70*4882a593Smuzhiyun VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 71*4882a593Smuzhiyun VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 72*4882a593Smuzhiyun VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 73*4882a593Smuzhiyun VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 74*4882a593Smuzhiyun >; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 78*4882a593Smuzhiyun fsl,pins = < 79*4882a593Smuzhiyun VF610_PAD_PTB4__UART1_TX 0x21a2 80*4882a593Smuzhiyun VF610_PAD_PTB5__UART1_RX 0x21a1 81*4882a593Smuzhiyun >; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&uart1 { 87*4882a593Smuzhiyun pinctrl-names = "default"; 88*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 89*4882a593Smuzhiyun status = "okay"; 90*4882a593Smuzhiyun}; 91