1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 5*4882a593Smuzhiyun#include "tegra20.dtsi" 6*4882a593Smuzhiyun#include "tegra20-cpu-opp.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun model = "Compulab TrimSlice board"; 10*4882a593Smuzhiyun compatible = "compulab,trimslice", "nvidia,tegra20"; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun aliases { 13*4882a593Smuzhiyun rtc0 = "/i2c@7000c500/rtc@56"; 14*4882a593Smuzhiyun rtc1 = "/rtc@7000e000"; 15*4882a593Smuzhiyun serial0 = &uarta; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun chosen { 19*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun memory@0 { 23*4882a593Smuzhiyun reg = <0x00000000 0x40000000>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun host1x@50000000 { 27*4882a593Smuzhiyun hdmi@54280000 { 28*4882a593Smuzhiyun status = "okay"; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun vdd-supply = <&hdmi_vdd_reg>; 31*4882a593Smuzhiyun pll-supply = <&hdmi_pll_reg>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun nvidia,ddc-i2c-bus = <&hdmi_ddc>; 34*4882a593Smuzhiyun nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 35*4882a593Smuzhiyun GPIO_ACTIVE_HIGH>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun pinmux@70000014 { 40*4882a593Smuzhiyun pinctrl-names = "default"; 41*4882a593Smuzhiyun pinctrl-0 = <&state_default>; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun state_default: pinmux { 44*4882a593Smuzhiyun ata { 45*4882a593Smuzhiyun nvidia,pins = "ata"; 46*4882a593Smuzhiyun nvidia,function = "ide"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun atb { 49*4882a593Smuzhiyun nvidia,pins = "atb", "gma"; 50*4882a593Smuzhiyun nvidia,function = "sdio4"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun atc { 53*4882a593Smuzhiyun nvidia,pins = "atc", "gmb"; 54*4882a593Smuzhiyun nvidia,function = "nand"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun atd { 57*4882a593Smuzhiyun nvidia,pins = "atd", "ate", "gme", "pta"; 58*4882a593Smuzhiyun nvidia,function = "gmi"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun cdev1 { 61*4882a593Smuzhiyun nvidia,pins = "cdev1"; 62*4882a593Smuzhiyun nvidia,function = "plla_out"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun cdev2 { 65*4882a593Smuzhiyun nvidia,pins = "cdev2"; 66*4882a593Smuzhiyun nvidia,function = "pllp_out4"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun crtp { 69*4882a593Smuzhiyun nvidia,pins = "crtp"; 70*4882a593Smuzhiyun nvidia,function = "crt"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun csus { 73*4882a593Smuzhiyun nvidia,pins = "csus"; 74*4882a593Smuzhiyun nvidia,function = "vi_sensor_clk"; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun dap1 { 77*4882a593Smuzhiyun nvidia,pins = "dap1"; 78*4882a593Smuzhiyun nvidia,function = "dap1"; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun dap2 { 81*4882a593Smuzhiyun nvidia,pins = "dap2"; 82*4882a593Smuzhiyun nvidia,function = "dap2"; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun dap3 { 85*4882a593Smuzhiyun nvidia,pins = "dap3"; 86*4882a593Smuzhiyun nvidia,function = "dap3"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun dap4 { 89*4882a593Smuzhiyun nvidia,pins = "dap4"; 90*4882a593Smuzhiyun nvidia,function = "dap4"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun ddc { 93*4882a593Smuzhiyun nvidia,pins = "ddc"; 94*4882a593Smuzhiyun nvidia,function = "i2c2"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun dta { 97*4882a593Smuzhiyun nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 98*4882a593Smuzhiyun nvidia,function = "vi"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun dtf { 101*4882a593Smuzhiyun nvidia,pins = "dtf"; 102*4882a593Smuzhiyun nvidia,function = "i2c3"; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun gmc { 105*4882a593Smuzhiyun nvidia,pins = "gmc", "gmd"; 106*4882a593Smuzhiyun nvidia,function = "sflash"; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun gpu { 109*4882a593Smuzhiyun nvidia,pins = "gpu"; 110*4882a593Smuzhiyun nvidia,function = "uarta"; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun gpu7 { 113*4882a593Smuzhiyun nvidia,pins = "gpu7"; 114*4882a593Smuzhiyun nvidia,function = "rtck"; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun gpv { 117*4882a593Smuzhiyun nvidia,pins = "gpv", "slxa", "slxk"; 118*4882a593Smuzhiyun nvidia,function = "pcie"; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun hdint { 121*4882a593Smuzhiyun nvidia,pins = "hdint"; 122*4882a593Smuzhiyun nvidia,function = "hdmi"; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun i2cp { 125*4882a593Smuzhiyun nvidia,pins = "i2cp"; 126*4882a593Smuzhiyun nvidia,function = "i2cp"; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun irrx { 129*4882a593Smuzhiyun nvidia,pins = "irrx", "irtx"; 130*4882a593Smuzhiyun nvidia,function = "uartb"; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun kbca { 133*4882a593Smuzhiyun nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 134*4882a593Smuzhiyun "kbce", "kbcf"; 135*4882a593Smuzhiyun nvidia,function = "kbc"; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun lcsn { 138*4882a593Smuzhiyun nvidia,pins = "lcsn", "ld0", "ld1", "ld2", 139*4882a593Smuzhiyun "ld3", "ld4", "ld5", "ld6", "ld7", 140*4882a593Smuzhiyun "ld8", "ld9", "ld10", "ld11", "ld12", 141*4882a593Smuzhiyun "ld13", "ld14", "ld15", "ld16", "ld17", 142*4882a593Smuzhiyun "ldc", "ldi", "lhp0", "lhp1", "lhp2", 143*4882a593Smuzhiyun "lhs", "lm0", "lm1", "lpp", "lpw0", 144*4882a593Smuzhiyun "lpw1", "lpw2", "lsc0", "lsc1", "lsck", 145*4882a593Smuzhiyun "lsda", "lsdi", "lspi", "lvp0", "lvp1", 146*4882a593Smuzhiyun "lvs"; 147*4882a593Smuzhiyun nvidia,function = "displaya"; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun owc { 150*4882a593Smuzhiyun nvidia,pins = "owc", "uac"; 151*4882a593Smuzhiyun nvidia,function = "rsvd2"; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun pmc { 154*4882a593Smuzhiyun nvidia,pins = "pmc"; 155*4882a593Smuzhiyun nvidia,function = "pwr_on"; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun rm { 158*4882a593Smuzhiyun nvidia,pins = "rm"; 159*4882a593Smuzhiyun nvidia,function = "i2c1"; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun sdb { 162*4882a593Smuzhiyun nvidia,pins = "sdb", "sdc", "sdd"; 163*4882a593Smuzhiyun nvidia,function = "pwm"; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun sdio1 { 166*4882a593Smuzhiyun nvidia,pins = "sdio1"; 167*4882a593Smuzhiyun nvidia,function = "sdio1"; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun slxc { 170*4882a593Smuzhiyun nvidia,pins = "slxc", "slxd"; 171*4882a593Smuzhiyun nvidia,function = "sdio3"; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun spdi { 174*4882a593Smuzhiyun nvidia,pins = "spdi", "spdo"; 175*4882a593Smuzhiyun nvidia,function = "spdif"; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun spia { 178*4882a593Smuzhiyun nvidia,pins = "spia", "spib", "spic"; 179*4882a593Smuzhiyun nvidia,function = "spi2"; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun spid { 182*4882a593Smuzhiyun nvidia,pins = "spid", "spie", "spif"; 183*4882a593Smuzhiyun nvidia,function = "spi1"; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun spig { 186*4882a593Smuzhiyun nvidia,pins = "spig", "spih"; 187*4882a593Smuzhiyun nvidia,function = "spi2_alt"; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun uaa { 190*4882a593Smuzhiyun nvidia,pins = "uaa", "uab", "uda"; 191*4882a593Smuzhiyun nvidia,function = "ulpi"; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun uad { 194*4882a593Smuzhiyun nvidia,pins = "uad"; 195*4882a593Smuzhiyun nvidia,function = "irda"; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun uca { 198*4882a593Smuzhiyun nvidia,pins = "uca", "ucb"; 199*4882a593Smuzhiyun nvidia,function = "uartc"; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun conf_ata { 202*4882a593Smuzhiyun nvidia,pins = "ata", "atc", "atd", "ate", 203*4882a593Smuzhiyun "crtp", "dap2", "dap3", "dap4", "dta", 204*4882a593Smuzhiyun "dtb", "dtc", "dtd", "dte", "gmb", 205*4882a593Smuzhiyun "gme", "i2cp", "pta", "slxc", "slxd", 206*4882a593Smuzhiyun "spdi", "spdo", "uda"; 207*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 208*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun conf_atb { 211*4882a593Smuzhiyun nvidia,pins = "atb", "cdev1", "cdev2", "dap1", 212*4882a593Smuzhiyun "gma", "gmc", "gmd", "gpu", "gpu7", 213*4882a593Smuzhiyun "gpv", "sdio1", "slxa", "slxk", "uac"; 214*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 215*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun conf_ck32 { 218*4882a593Smuzhiyun nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 219*4882a593Smuzhiyun "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 220*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_NONE>; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun conf_csus { 223*4882a593Smuzhiyun nvidia,pins = "csus", "spia", "spib", 224*4882a593Smuzhiyun "spid", "spif"; 225*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 226*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun conf_ddc { 229*4882a593Smuzhiyun nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; 230*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 231*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun conf_hdint { 234*4882a593Smuzhiyun nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 235*4882a593Smuzhiyun "lpw1", "lsc1", "lsck", "lsda", "lsdi", 236*4882a593Smuzhiyun "lvp0", "pmc"; 237*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun conf_irrx { 240*4882a593Smuzhiyun nvidia,pins = "irrx", "irtx", "kbca", "kbcb", 241*4882a593Smuzhiyun "kbcc", "kbcd", "kbce", "kbcf", "owc", 242*4882a593Smuzhiyun "spic", "spie", "spig", "spih", "uaa", 243*4882a593Smuzhiyun "uab", "uad", "uca", "ucb"; 244*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 245*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_ENABLE>; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun conf_lc { 248*4882a593Smuzhiyun nvidia,pins = "lc", "ls"; 249*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_UP>; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun conf_ld0 { 252*4882a593Smuzhiyun nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 253*4882a593Smuzhiyun "ld5", "ld6", "ld7", "ld8", "ld9", 254*4882a593Smuzhiyun "ld10", "ld11", "ld12", "ld13", "ld14", 255*4882a593Smuzhiyun "ld15", "ld16", "ld17", "ldi", "lhp0", 256*4882a593Smuzhiyun "lhp1", "lhp2", "lhs", "lm0", "lpp", 257*4882a593Smuzhiyun "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 258*4882a593Smuzhiyun "lvs", "sdb"; 259*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun conf_ld17_0 { 262*4882a593Smuzhiyun nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 263*4882a593Smuzhiyun "ld23_22"; 264*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun conf_spif { 267*4882a593Smuzhiyun nvidia,pins = "spif"; 268*4882a593Smuzhiyun nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 269*4882a593Smuzhiyun nvidia,tristate = <TEGRA_PIN_DISABLE>; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun i2s@70002800 { 275*4882a593Smuzhiyun status = "okay"; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun serial@70006000 { 279*4882a593Smuzhiyun status = "okay"; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun dvi_ddc: i2c@7000c000 { 283*4882a593Smuzhiyun status = "okay"; 284*4882a593Smuzhiyun clock-frequency = <100000>; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun spi@7000c380 { 288*4882a593Smuzhiyun status = "okay"; 289*4882a593Smuzhiyun spi-max-frequency = <48000000>; 290*4882a593Smuzhiyun spi-flash@0 { 291*4882a593Smuzhiyun compatible = "winbond,w25q80bl", "jedec,spi-nor"; 292*4882a593Smuzhiyun reg = <0>; 293*4882a593Smuzhiyun spi-max-frequency = <48000000>; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun hdmi_ddc: i2c@7000c400 { 298*4882a593Smuzhiyun status = "okay"; 299*4882a593Smuzhiyun clock-frequency = <100000>; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun i2c@7000c500 { 303*4882a593Smuzhiyun status = "okay"; 304*4882a593Smuzhiyun clock-frequency = <400000>; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun codec: codec@1a { 307*4882a593Smuzhiyun compatible = "ti,tlv320aic23"; 308*4882a593Smuzhiyun reg = <0x1a>; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun rtc@56 { 312*4882a593Smuzhiyun compatible = "emmicro,em3027"; 313*4882a593Smuzhiyun reg = <0x56>; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun pmc@7000e400 { 318*4882a593Smuzhiyun nvidia,suspend-mode = <1>; 319*4882a593Smuzhiyun nvidia,cpu-pwr-good-time = <5000>; 320*4882a593Smuzhiyun nvidia,cpu-pwr-off-time = <5000>; 321*4882a593Smuzhiyun nvidia,core-pwr-good-time = <3845 3845>; 322*4882a593Smuzhiyun nvidia,core-pwr-off-time = <3875>; 323*4882a593Smuzhiyun nvidia,sys-clock-req-active-high; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun pcie@80003000 { 327*4882a593Smuzhiyun status = "okay"; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun avdd-pex-supply = <&pci_vdd_reg>; 330*4882a593Smuzhiyun vdd-pex-supply = <&pci_vdd_reg>; 331*4882a593Smuzhiyun avdd-pex-pll-supply = <&pci_vdd_reg>; 332*4882a593Smuzhiyun avdd-plle-supply = <&pci_vdd_reg>; 333*4882a593Smuzhiyun vddio-pex-clk-supply = <&pci_clk_reg>; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun pci@1,0 { 336*4882a593Smuzhiyun status = "okay"; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun usb@c5000000 { 341*4882a593Smuzhiyun status = "okay"; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun usb-phy@c5000000 { 345*4882a593Smuzhiyun status = "okay"; 346*4882a593Smuzhiyun vbus-supply = <&vbus_reg>; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun usb@c5004000 { 350*4882a593Smuzhiyun status = "okay"; 351*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 352*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun usb-phy@c5004000 { 356*4882a593Smuzhiyun status = "okay"; 357*4882a593Smuzhiyun nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 358*4882a593Smuzhiyun GPIO_ACTIVE_LOW>; 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun usb@c5008000 { 362*4882a593Smuzhiyun status = "okay"; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun usb-phy@c5008000 { 366*4882a593Smuzhiyun status = "okay"; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun mmc@c8000000 { 370*4882a593Smuzhiyun status = "okay"; 371*4882a593Smuzhiyun broken-cd; 372*4882a593Smuzhiyun bus-width = <4>; 373*4882a593Smuzhiyun }; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun mmc@c8000600 { 376*4882a593Smuzhiyun status = "okay"; 377*4882a593Smuzhiyun cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; 378*4882a593Smuzhiyun wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; 379*4882a593Smuzhiyun bus-width = <4>; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun clk32k_in: clock@0 { 383*4882a593Smuzhiyun compatible = "fixed-clock"; 384*4882a593Smuzhiyun clock-frequency = <32768>; 385*4882a593Smuzhiyun #clock-cells = <0>; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun gpio-keys { 389*4882a593Smuzhiyun compatible = "gpio-keys"; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun power { 392*4882a593Smuzhiyun label = "Power"; 393*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 394*4882a593Smuzhiyun linux,code = <KEY_POWER>; 395*4882a593Smuzhiyun wakeup-source; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun }; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun poweroff { 400*4882a593Smuzhiyun compatible = "gpio-poweroff"; 401*4882a593Smuzhiyun gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun hdmi_vdd_reg: regulator@0 { 405*4882a593Smuzhiyun compatible = "regulator-fixed"; 406*4882a593Smuzhiyun regulator-name = "avdd_hdmi"; 407*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 408*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 409*4882a593Smuzhiyun regulator-always-on; 410*4882a593Smuzhiyun }; 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun hdmi_pll_reg: regulator@1 { 413*4882a593Smuzhiyun compatible = "regulator-fixed"; 414*4882a593Smuzhiyun regulator-name = "avdd_hdmi_pll"; 415*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 416*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 417*4882a593Smuzhiyun regulator-always-on; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun vbus_reg: regulator@2 { 421*4882a593Smuzhiyun compatible = "regulator-fixed"; 422*4882a593Smuzhiyun regulator-name = "usb1_vbus"; 423*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 424*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 425*4882a593Smuzhiyun enable-active-high; 426*4882a593Smuzhiyun gpio = <&gpio TEGRA_GPIO(V, 2) 0>; 427*4882a593Smuzhiyun regulator-always-on; 428*4882a593Smuzhiyun regulator-boot-on; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun pci_clk_reg: regulator@3 { 432*4882a593Smuzhiyun compatible = "regulator-fixed"; 433*4882a593Smuzhiyun regulator-name = "pci_clk"; 434*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 435*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 436*4882a593Smuzhiyun regulator-always-on; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun pci_vdd_reg: regulator@4 { 440*4882a593Smuzhiyun compatible = "regulator-fixed"; 441*4882a593Smuzhiyun regulator-name = "pci_vdd"; 442*4882a593Smuzhiyun regulator-min-microvolt = <1050000>; 443*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 444*4882a593Smuzhiyun regulator-always-on; 445*4882a593Smuzhiyun }; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun sound { 448*4882a593Smuzhiyun compatible = "nvidia,tegra-audio-trimslice"; 449*4882a593Smuzhiyun nvidia,i2s-controller = <&tegra_i2s1>; 450*4882a593Smuzhiyun nvidia,audio-codec = <&codec>; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 453*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 454*4882a593Smuzhiyun <&tegra_car TEGRA20_CLK_CDEV1>; 455*4882a593Smuzhiyun clock-names = "pll_a", "pll_a_out0", "mclk"; 456*4882a593Smuzhiyun }; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun cpus { 459*4882a593Smuzhiyun cpu0: cpu@0 { 460*4882a593Smuzhiyun operating-points-v2 = <&cpu0_opp_table>; 461*4882a593Smuzhiyun }; 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun cpu@1 { 464*4882a593Smuzhiyun operating-points-v2 = <&cpu0_opp_table>; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun}; 468