xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/tegra20-acer-a500-picasso.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/dts-v1/;
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun#include <dt-bindings/input/gpio-keys.h>
5*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
6*4882a593Smuzhiyun#include <dt-bindings/thermal/thermal.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "tegra20.dtsi"
9*4882a593Smuzhiyun#include "tegra20-cpu-opp.dtsi"
10*4882a593Smuzhiyun#include "tegra20-cpu-opp-microvolt.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Acer Iconia Tab A500";
14*4882a593Smuzhiyun	compatible = "acer,picasso", "nvidia,tegra20";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	aliases {
17*4882a593Smuzhiyun		mmc0 = &sdmmc4; /* eMMC */
18*4882a593Smuzhiyun		mmc1 = &sdmmc3; /* MicroSD */
19*4882a593Smuzhiyun		mmc2 = &sdmmc1; /* WiFi */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		rtc0 = &pmic;
22*4882a593Smuzhiyun		rtc1 = "/rtc@7000e000";
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun		serial0 = &uartd; /* Docking station */
25*4882a593Smuzhiyun		serial1 = &uartc; /* Bluetooth */
26*4882a593Smuzhiyun		serial2 = &uartb; /* GPS */
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	/*
30*4882a593Smuzhiyun	 * The decompressor and also some bootloaders rely on a
31*4882a593Smuzhiyun	 * pre-existing /chosen node to be available to insert the
32*4882a593Smuzhiyun	 * command line and merge other ATAGS info.
33*4882a593Smuzhiyun	 */
34*4882a593Smuzhiyun	chosen {};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	memory@0 {
37*4882a593Smuzhiyun		reg = <0x00000000 0x40000000>;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	reserved-memory {
41*4882a593Smuzhiyun		#address-cells = <1>;
42*4882a593Smuzhiyun		#size-cells = <1>;
43*4882a593Smuzhiyun		ranges;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		ramoops@2ffe0000 {
46*4882a593Smuzhiyun			compatible = "ramoops";
47*4882a593Smuzhiyun			reg = <0x2ffe0000 0x10000>;	/* 64kB */
48*4882a593Smuzhiyun			console-size = <0x8000>;	/* 32kB */
49*4882a593Smuzhiyun			record-size = <0x400>;		/*  1kB */
50*4882a593Smuzhiyun			ecc-size = <16>;
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun		linux,cma@30000000 {
54*4882a593Smuzhiyun			compatible = "shared-dma-pool";
55*4882a593Smuzhiyun			alloc-ranges = <0x30000000 0x10000000>;
56*4882a593Smuzhiyun			size = <0x10000000>; /* 256MiB */
57*4882a593Smuzhiyun			linux,cma-default;
58*4882a593Smuzhiyun			reusable;
59*4882a593Smuzhiyun		};
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	host1x@50000000 {
63*4882a593Smuzhiyun		dc@54200000 {
64*4882a593Smuzhiyun			rgb {
65*4882a593Smuzhiyun				status = "okay";
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun				port@0 {
68*4882a593Smuzhiyun					lcd_output: endpoint {
69*4882a593Smuzhiyun						remote-endpoint = <&lvds_encoder_input>;
70*4882a593Smuzhiyun						bus-width = <18>;
71*4882a593Smuzhiyun					};
72*4882a593Smuzhiyun				};
73*4882a593Smuzhiyun			};
74*4882a593Smuzhiyun		};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun		hdmi@54280000 {
77*4882a593Smuzhiyun			status = "okay";
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun			vdd-supply = <&hdmi_vdd_reg>;
80*4882a593Smuzhiyun			pll-supply = <&hdmi_pll_reg>;
81*4882a593Smuzhiyun			hdmi-supply = <&vdd_5v0_sys>;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
84*4882a593Smuzhiyun			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
85*4882a593Smuzhiyun				GPIO_ACTIVE_HIGH>;
86*4882a593Smuzhiyun		};
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	pinmux@70000014 {
90*4882a593Smuzhiyun		pinctrl-names = "default";
91*4882a593Smuzhiyun		pinctrl-0 = <&state_default>;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		state_default: pinmux {
94*4882a593Smuzhiyun			ata {
95*4882a593Smuzhiyun				nvidia,pins = "ata";
96*4882a593Smuzhiyun				nvidia,function = "ide";
97*4882a593Smuzhiyun			};
98*4882a593Smuzhiyun			atb {
99*4882a593Smuzhiyun				nvidia,pins = "atb", "gma", "gme";
100*4882a593Smuzhiyun				nvidia,function = "sdio4";
101*4882a593Smuzhiyun			};
102*4882a593Smuzhiyun			atc {
103*4882a593Smuzhiyun				nvidia,pins = "atc";
104*4882a593Smuzhiyun				nvidia,function = "nand";
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun			atd {
107*4882a593Smuzhiyun				nvidia,pins = "atd", "ate", "gmb", "spia",
108*4882a593Smuzhiyun					"spib", "spic";
109*4882a593Smuzhiyun				nvidia,function = "gmi";
110*4882a593Smuzhiyun			};
111*4882a593Smuzhiyun			cdev1 {
112*4882a593Smuzhiyun				nvidia,pins = "cdev1";
113*4882a593Smuzhiyun				nvidia,function = "plla_out";
114*4882a593Smuzhiyun			};
115*4882a593Smuzhiyun			cdev2 {
116*4882a593Smuzhiyun				nvidia,pins = "cdev2";
117*4882a593Smuzhiyun				nvidia,function = "pllp_out4";
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun			crtp {
120*4882a593Smuzhiyun				nvidia,pins = "crtp", "lm1";
121*4882a593Smuzhiyun				nvidia,function = "crt";
122*4882a593Smuzhiyun			};
123*4882a593Smuzhiyun			csus {
124*4882a593Smuzhiyun				nvidia,pins = "csus";
125*4882a593Smuzhiyun				nvidia,function = "vi_sensor_clk";
126*4882a593Smuzhiyun			};
127*4882a593Smuzhiyun			dap1 {
128*4882a593Smuzhiyun				nvidia,pins = "dap1";
129*4882a593Smuzhiyun				nvidia,function = "dap1";
130*4882a593Smuzhiyun			};
131*4882a593Smuzhiyun			dap2 {
132*4882a593Smuzhiyun				nvidia,pins = "dap2";
133*4882a593Smuzhiyun				nvidia,function = "dap2";
134*4882a593Smuzhiyun			};
135*4882a593Smuzhiyun			dap3 {
136*4882a593Smuzhiyun				nvidia,pins = "dap3";
137*4882a593Smuzhiyun				nvidia,function = "dap3";
138*4882a593Smuzhiyun			};
139*4882a593Smuzhiyun			dap4 {
140*4882a593Smuzhiyun				nvidia,pins = "dap4";
141*4882a593Smuzhiyun				nvidia,function = "dap4";
142*4882a593Smuzhiyun			};
143*4882a593Smuzhiyun			dta {
144*4882a593Smuzhiyun				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
145*4882a593Smuzhiyun				nvidia,function = "vi";
146*4882a593Smuzhiyun			};
147*4882a593Smuzhiyun			dtf {
148*4882a593Smuzhiyun				nvidia,pins = "dtf";
149*4882a593Smuzhiyun				nvidia,function = "i2c3";
150*4882a593Smuzhiyun			};
151*4882a593Smuzhiyun			gmc {
152*4882a593Smuzhiyun				nvidia,pins = "gmc";
153*4882a593Smuzhiyun				nvidia,function = "uartd";
154*4882a593Smuzhiyun			};
155*4882a593Smuzhiyun			gmd {
156*4882a593Smuzhiyun				nvidia,pins = "gmd";
157*4882a593Smuzhiyun				nvidia,function = "sflash";
158*4882a593Smuzhiyun			};
159*4882a593Smuzhiyun			gpu {
160*4882a593Smuzhiyun				nvidia,pins = "gpu";
161*4882a593Smuzhiyun				nvidia,function = "pwm";
162*4882a593Smuzhiyun			};
163*4882a593Smuzhiyun			gpu7 {
164*4882a593Smuzhiyun				nvidia,pins = "gpu7";
165*4882a593Smuzhiyun				nvidia,function = "rtck";
166*4882a593Smuzhiyun			};
167*4882a593Smuzhiyun			gpv {
168*4882a593Smuzhiyun				nvidia,pins = "gpv", "slxa";
169*4882a593Smuzhiyun				nvidia,function = "pcie";
170*4882a593Smuzhiyun			};
171*4882a593Smuzhiyun			hdint {
172*4882a593Smuzhiyun				nvidia,pins = "hdint";
173*4882a593Smuzhiyun				nvidia,function = "hdmi";
174*4882a593Smuzhiyun			};
175*4882a593Smuzhiyun			i2cp {
176*4882a593Smuzhiyun				nvidia,pins = "i2cp";
177*4882a593Smuzhiyun				nvidia,function = "i2cp";
178*4882a593Smuzhiyun			};
179*4882a593Smuzhiyun			irrx {
180*4882a593Smuzhiyun				nvidia,pins = "irrx", "irtx";
181*4882a593Smuzhiyun				nvidia,function = "uartb";
182*4882a593Smuzhiyun			};
183*4882a593Smuzhiyun			kbca {
184*4882a593Smuzhiyun				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
185*4882a593Smuzhiyun					"kbce", "kbcf";
186*4882a593Smuzhiyun				nvidia,function = "kbc";
187*4882a593Smuzhiyun			};
188*4882a593Smuzhiyun			lcsn {
189*4882a593Smuzhiyun				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
190*4882a593Smuzhiyun					"lsdi", "lvp0";
191*4882a593Smuzhiyun				nvidia,function = "rsvd4";
192*4882a593Smuzhiyun			};
193*4882a593Smuzhiyun			ld0 {
194*4882a593Smuzhiyun				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
195*4882a593Smuzhiyun					"ld5", "ld6", "ld7", "ld8", "ld9",
196*4882a593Smuzhiyun					"ld10", "ld11", "ld12", "ld13", "ld14",
197*4882a593Smuzhiyun					"ld15", "ld16", "ld17", "ldi", "lhp0",
198*4882a593Smuzhiyun					"lhp1", "lhp2", "lhs", "lpp", "lsc0",
199*4882a593Smuzhiyun					"lsc1", "lsck", "lsda", "lspi", "lvp1",
200*4882a593Smuzhiyun					"lvs";
201*4882a593Smuzhiyun				nvidia,function = "displaya";
202*4882a593Smuzhiyun			};
203*4882a593Smuzhiyun			owc {
204*4882a593Smuzhiyun				nvidia,pins = "owc", "spdi", "spdo", "uac";
205*4882a593Smuzhiyun				nvidia,function = "rsvd2";
206*4882a593Smuzhiyun			};
207*4882a593Smuzhiyun			pmc {
208*4882a593Smuzhiyun				nvidia,pins = "pmc";
209*4882a593Smuzhiyun				nvidia,function = "pwr_on";
210*4882a593Smuzhiyun			};
211*4882a593Smuzhiyun			rm {
212*4882a593Smuzhiyun				nvidia,pins = "rm";
213*4882a593Smuzhiyun				nvidia,function = "i2c1";
214*4882a593Smuzhiyun			};
215*4882a593Smuzhiyun			sdb {
216*4882a593Smuzhiyun				nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
217*4882a593Smuzhiyun				nvidia,function = "sdio3";
218*4882a593Smuzhiyun			};
219*4882a593Smuzhiyun			sdio1 {
220*4882a593Smuzhiyun				nvidia,pins = "sdio1";
221*4882a593Smuzhiyun				nvidia,function = "sdio1";
222*4882a593Smuzhiyun			};
223*4882a593Smuzhiyun			slxd {
224*4882a593Smuzhiyun				nvidia,pins = "slxd";
225*4882a593Smuzhiyun				nvidia,function = "spdif";
226*4882a593Smuzhiyun			};
227*4882a593Smuzhiyun			spid {
228*4882a593Smuzhiyun				nvidia,pins = "spid", "spie", "spif";
229*4882a593Smuzhiyun				nvidia,function = "spi1";
230*4882a593Smuzhiyun			};
231*4882a593Smuzhiyun			spig {
232*4882a593Smuzhiyun				nvidia,pins = "spig", "spih";
233*4882a593Smuzhiyun				nvidia,function = "spi2_alt";
234*4882a593Smuzhiyun			};
235*4882a593Smuzhiyun			uaa {
236*4882a593Smuzhiyun				nvidia,pins = "uaa", "uab", "uda";
237*4882a593Smuzhiyun				nvidia,function = "ulpi";
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun			uad {
240*4882a593Smuzhiyun				nvidia,pins = "uad";
241*4882a593Smuzhiyun				nvidia,function = "irda";
242*4882a593Smuzhiyun			};
243*4882a593Smuzhiyun			uca {
244*4882a593Smuzhiyun				nvidia,pins = "uca", "ucb";
245*4882a593Smuzhiyun				nvidia,function = "uartc";
246*4882a593Smuzhiyun			};
247*4882a593Smuzhiyun			conf_ata {
248*4882a593Smuzhiyun				nvidia,pins = "ata", "atb", "atc", "atd",
249*4882a593Smuzhiyun					"cdev1", "cdev2", "csus", "dap1",
250*4882a593Smuzhiyun					"dap4", "dte", "dtf", "gma", "gmc",
251*4882a593Smuzhiyun					"gme", "gpu", "gpu7", "gpv", "i2cp",
252*4882a593Smuzhiyun					"irrx", "irtx", "pta", "rm",
253*4882a593Smuzhiyun					"sdc", "sdd", "slxc", "slxd", "slxk",
254*4882a593Smuzhiyun					"spdi", "spdo", "uac", "uad", "uda";
255*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
257*4882a593Smuzhiyun			};
258*4882a593Smuzhiyun			conf_ate {
259*4882a593Smuzhiyun				nvidia,pins = "ate", "dap2", "dap3",
260*4882a593Smuzhiyun					"gmd", "owc", "spia", "spib", "spic",
261*4882a593Smuzhiyun					"spid", "spie";
262*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
263*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
264*4882a593Smuzhiyun			};
265*4882a593Smuzhiyun			conf_ck32 {
266*4882a593Smuzhiyun				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
267*4882a593Smuzhiyun					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
268*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269*4882a593Smuzhiyun			};
270*4882a593Smuzhiyun			conf_crtp {
271*4882a593Smuzhiyun				nvidia,pins = "crtp", "gmb", "slxa", "spig",
272*4882a593Smuzhiyun					"spih";
273*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
274*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
275*4882a593Smuzhiyun			};
276*4882a593Smuzhiyun			conf_dta {
277*4882a593Smuzhiyun				nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
278*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
279*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
280*4882a593Smuzhiyun			};
281*4882a593Smuzhiyun			conf_dte {
282*4882a593Smuzhiyun				nvidia,pins = "spif";
283*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
284*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
285*4882a593Smuzhiyun			};
286*4882a593Smuzhiyun			conf_hdint {
287*4882a593Smuzhiyun				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
288*4882a593Smuzhiyun					"lpw1", "lsck", "lsda", "lsdi",
289*4882a593Smuzhiyun					"lvp0";
290*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_ENABLE>;
291*4882a593Smuzhiyun			};
292*4882a593Smuzhiyun			conf_kbca {
293*4882a593Smuzhiyun				nvidia,pins = "kbca", "kbcc", "kbcd",
294*4882a593Smuzhiyun					"kbce", "kbcf", "sdio1", "uaa",
295*4882a593Smuzhiyun					"uab", "uca", "ucb";
296*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
297*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
298*4882a593Smuzhiyun			};
299*4882a593Smuzhiyun			conf_lc {
300*4882a593Smuzhiyun				nvidia,pins = "lc", "ls";
301*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_UP>;
302*4882a593Smuzhiyun			};
303*4882a593Smuzhiyun			conf_ld0 {
304*4882a593Smuzhiyun				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
305*4882a593Smuzhiyun					"ld5", "ld6", "ld7", "ld8", "ld9",
306*4882a593Smuzhiyun					"ld10", "ld11", "ld12", "ld13", "ld14",
307*4882a593Smuzhiyun					"ld15", "ld16", "ld17", "ldi", "lhp0",
308*4882a593Smuzhiyun					"lhp1", "lhp2", "lhs", "lm0", "lpp",
309*4882a593Smuzhiyun					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
310*4882a593Smuzhiyun					"lvp1", "lvs", "pmc", "sdb";
311*4882a593Smuzhiyun				nvidia,tristate = <TEGRA_PIN_DISABLE>;
312*4882a593Smuzhiyun			};
313*4882a593Smuzhiyun			conf_ld17_0 {
314*4882a593Smuzhiyun				nvidia,pins = "ld17_0";
315*4882a593Smuzhiyun				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316*4882a593Smuzhiyun			};
317*4882a593Smuzhiyun			drive_ddc {
318*4882a593Smuzhiyun				nvidia,pins = "drive_ddc",
319*4882a593Smuzhiyun						"drive_vi1",
320*4882a593Smuzhiyun						"drive_sdio1";
321*4882a593Smuzhiyun				nvidia,pull-up-strength = <31>;
322*4882a593Smuzhiyun				nvidia,pull-down-strength = <31>;
323*4882a593Smuzhiyun				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
324*4882a593Smuzhiyun				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
325*4882a593Smuzhiyun				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
326*4882a593Smuzhiyun				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
327*4882a593Smuzhiyun				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
328*4882a593Smuzhiyun			};
329*4882a593Smuzhiyun			drive_dbg {
330*4882a593Smuzhiyun				nvidia,pins = "drive_dbg",
331*4882a593Smuzhiyun						"drive_vi2",
332*4882a593Smuzhiyun						"drive_at1",
333*4882a593Smuzhiyun						"drive_ao1";
334*4882a593Smuzhiyun				nvidia,pull-up-strength = <31>;
335*4882a593Smuzhiyun				nvidia,pull-down-strength = <31>;
336*4882a593Smuzhiyun				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
337*4882a593Smuzhiyun				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
338*4882a593Smuzhiyun				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
339*4882a593Smuzhiyun				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
340*4882a593Smuzhiyun				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
341*4882a593Smuzhiyun			};
342*4882a593Smuzhiyun		};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun		state_i2cmux_ddc: pinmux_i2cmux_ddc {
345*4882a593Smuzhiyun			ddc {
346*4882a593Smuzhiyun				nvidia,pins = "ddc";
347*4882a593Smuzhiyun				nvidia,function = "i2c2";
348*4882a593Smuzhiyun			};
349*4882a593Smuzhiyun			pta {
350*4882a593Smuzhiyun				nvidia,pins = "pta";
351*4882a593Smuzhiyun				nvidia,function = "rsvd4";
352*4882a593Smuzhiyun			};
353*4882a593Smuzhiyun		};
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun		state_i2cmux_pta: pinmux_i2cmux_pta {
356*4882a593Smuzhiyun			ddc {
357*4882a593Smuzhiyun				nvidia,pins = "ddc";
358*4882a593Smuzhiyun				nvidia,function = "rsvd4";
359*4882a593Smuzhiyun			};
360*4882a593Smuzhiyun			pta {
361*4882a593Smuzhiyun				nvidia,pins = "pta";
362*4882a593Smuzhiyun				nvidia,function = "i2c2";
363*4882a593Smuzhiyun			};
364*4882a593Smuzhiyun		};
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun		state_i2cmux_idle: pinmux_i2cmux_idle {
367*4882a593Smuzhiyun			ddc {
368*4882a593Smuzhiyun				nvidia,pins = "ddc";
369*4882a593Smuzhiyun				nvidia,function = "rsvd4";
370*4882a593Smuzhiyun			};
371*4882a593Smuzhiyun			pta {
372*4882a593Smuzhiyun				nvidia,pins = "pta";
373*4882a593Smuzhiyun				nvidia,function = "rsvd4";
374*4882a593Smuzhiyun			};
375*4882a593Smuzhiyun		};
376*4882a593Smuzhiyun	};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun	tegra_i2s1: i2s@70002800 {
379*4882a593Smuzhiyun		status = "okay";
380*4882a593Smuzhiyun	};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun	uartb: serial@70006040 {
383*4882a593Smuzhiyun		compatible = "nvidia,tegra20-hsuart";
384*4882a593Smuzhiyun		/* GPS BCM4751 */
385*4882a593Smuzhiyun	};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun	uartc: serial@70006200 {
388*4882a593Smuzhiyun		compatible = "nvidia,tegra20-hsuart";
389*4882a593Smuzhiyun		status = "okay";
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun		/* Azurewave AW-NH665 BCM4329B1 */
392*4882a593Smuzhiyun		bluetooth {
393*4882a593Smuzhiyun			compatible = "brcm,bcm4329-bt";
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun			/* PLLP 216MHz / 16 / 4 */
396*4882a593Smuzhiyun			max-speed = <3375000>;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun			clocks = <&rtc_32k_wifi>;
399*4882a593Smuzhiyun			clock-names = "txco";
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun			vbat-supply  = <&vdd_3v3_sys>;
402*4882a593Smuzhiyun			vddio-supply = <&vdd_1v8_sys>;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
405*4882a593Smuzhiyun			host-wakeup-gpios =   <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
406*4882a593Smuzhiyun			shutdown-gpios =      <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
407*4882a593Smuzhiyun		};
408*4882a593Smuzhiyun	};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun	uartd: serial@70006300 {
411*4882a593Smuzhiyun		/* Docking station */
412*4882a593Smuzhiyun	};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun	i2c@7000c000 {
415*4882a593Smuzhiyun		clock-frequency = <400000>;
416*4882a593Smuzhiyun		status = "okay";
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun		wm8903: audio-codec@1a {
419*4882a593Smuzhiyun			compatible = "wlf,wm8903";
420*4882a593Smuzhiyun			reg = <0x1a>;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
423*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun			gpio-controller;
426*4882a593Smuzhiyun			#gpio-cells = <2>;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun			gpio-cfg = <
429*4882a593Smuzhiyun				0x0000 /* MIC_LR_OUT#    GPIO, output, low */
430*4882a593Smuzhiyun				0x0000 /* FM2018-enable  GPIO, output, low */
431*4882a593Smuzhiyun				0x0000 /* Speaker-enable GPIO, output, low */
432*4882a593Smuzhiyun				0x0200 /* Interrupt, output */
433*4882a593Smuzhiyun				0x01a0 /* BCLK, input, active high */
434*4882a593Smuzhiyun			>;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun			AVDD-supply  = <&vdd_1v8_sys>;
437*4882a593Smuzhiyun			CPVDD-supply = <&vdd_1v8_sys>;
438*4882a593Smuzhiyun			DBVDD-supply = <&vdd_1v8_sys>;
439*4882a593Smuzhiyun			DCVDD-supply = <&vdd_1v8_sys>;
440*4882a593Smuzhiyun		};
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun		touchscreen@4c {
443*4882a593Smuzhiyun			compatible = "atmel,maxtouch";
444*4882a593Smuzhiyun			reg = <0x4c>;
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
447*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun			reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun			vdda-supply = <&vdd_3v3_sys>;
452*4882a593Smuzhiyun			vdd-supply  = <&vdd_3v3_sys>;
453*4882a593Smuzhiyun		};
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun		gyroscope@68 {
456*4882a593Smuzhiyun			compatible = "invensense,mpu3050";
457*4882a593Smuzhiyun			reg = <0x68>;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
460*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun			vdd-supply    = <&vdd_3v3_sys>;
463*4882a593Smuzhiyun			vlogic-supply = <&vdd_1v8_sys>;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun			mount-matrix =	 "0",  "1",  "0",
466*4882a593Smuzhiyun					 "1",  "0",  "0",
467*4882a593Smuzhiyun					 "0",  "0", "-1";
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun			i2c-gate {
470*4882a593Smuzhiyun				#address-cells = <1>;
471*4882a593Smuzhiyun				#size-cells = <0>;
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun				accelerometer@f {
474*4882a593Smuzhiyun					compatible = "kionix,kxtf9";
475*4882a593Smuzhiyun					reg = <0x0f>;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun					interrupt-parent = <&gpio>;
478*4882a593Smuzhiyun					interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun					mount-matrix =	 "0",  "1",  "0",
481*4882a593Smuzhiyun							 "1",  "0",  "0",
482*4882a593Smuzhiyun							 "0",  "0", "-1";
483*4882a593Smuzhiyun				};
484*4882a593Smuzhiyun			};
485*4882a593Smuzhiyun		};
486*4882a593Smuzhiyun	};
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun	i2c@7000c400 {
489*4882a593Smuzhiyun		clock-frequency = <10000>;
490*4882a593Smuzhiyun		status = "okay";
491*4882a593Smuzhiyun	};
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun	i2cmux {
494*4882a593Smuzhiyun		compatible = "i2c-mux-pinctrl";
495*4882a593Smuzhiyun		#address-cells = <1>;
496*4882a593Smuzhiyun		#size-cells = <0>;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun		i2c-parent = <&{/i2c@7000c400}>;
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun		pinctrl-names = "ddc", "pta", "idle";
501*4882a593Smuzhiyun		pinctrl-0 = <&state_i2cmux_ddc>;
502*4882a593Smuzhiyun		pinctrl-1 = <&state_i2cmux_pta>;
503*4882a593Smuzhiyun		pinctrl-2 = <&state_i2cmux_idle>;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun		hdmi_ddc: i2c@0 {
506*4882a593Smuzhiyun			reg = <0>;
507*4882a593Smuzhiyun			#address-cells = <1>;
508*4882a593Smuzhiyun			#size-cells = <0>;
509*4882a593Smuzhiyun		};
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun		panel_ddc: i2c@1 {
512*4882a593Smuzhiyun			reg = <1>;
513*4882a593Smuzhiyun			#address-cells = <1>;
514*4882a593Smuzhiyun			#size-cells = <0>;
515*4882a593Smuzhiyun		};
516*4882a593Smuzhiyun	};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun	pwm: pwm@7000a000 {
519*4882a593Smuzhiyun		status = "okay";
520*4882a593Smuzhiyun	};
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun	i2c@7000d000 {
523*4882a593Smuzhiyun		clock-frequency = <100000>;
524*4882a593Smuzhiyun		status = "okay";
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun		magnetometer@c {
527*4882a593Smuzhiyun			compatible = "ak,ak8975";
528*4882a593Smuzhiyun			reg = <0x0c>;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
531*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun			vdd-supply = <&vdd_3v3_sys>;
534*4882a593Smuzhiyun			vid-supply = <&vdd_1v8_sys>;
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun			mount-matrix =	"1",  "0",  "0",
537*4882a593Smuzhiyun					"0", "-1",  "0",
538*4882a593Smuzhiyun					"0",  "0", "-1";
539*4882a593Smuzhiyun		};
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun		pmic: pmic@34 {
542*4882a593Smuzhiyun			compatible = "ti,tps6586x";
543*4882a593Smuzhiyun			reg = <0x34>;
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun			#gpio-cells = <2>;
548*4882a593Smuzhiyun			gpio-controller;
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun			sys-supply       = <&vdd_5v0_sys>;
551*4882a593Smuzhiyun			vin-sm0-supply   = <&sys_reg>;
552*4882a593Smuzhiyun			vin-sm1-supply   = <&sys_reg>;
553*4882a593Smuzhiyun			vin-sm2-supply   = <&sys_reg>;
554*4882a593Smuzhiyun			vinldo01-supply  = <&sm2_reg>;
555*4882a593Smuzhiyun			vinldo23-supply  = <&sm2_reg>;
556*4882a593Smuzhiyun			vinldo4-supply   = <&sm2_reg>;
557*4882a593Smuzhiyun			vinldo678-supply = <&sm2_reg>;
558*4882a593Smuzhiyun			vinldo9-supply   = <&sm2_reg>;
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun			regulators {
561*4882a593Smuzhiyun				sys_reg: sys {
562*4882a593Smuzhiyun					regulator-name = "vdd_sys";
563*4882a593Smuzhiyun					regulator-always-on;
564*4882a593Smuzhiyun				};
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun				vdd_core: sm0 {
567*4882a593Smuzhiyun					regulator-name = "vdd_sm0,vdd_core";
568*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
569*4882a593Smuzhiyun					regulator-max-microvolt = <1300000>;
570*4882a593Smuzhiyun					regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
571*4882a593Smuzhiyun					regulator-coupled-max-spread = <170000 550000>;
572*4882a593Smuzhiyun					regulator-always-on;
573*4882a593Smuzhiyun					regulator-boot-on;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun					nvidia,tegra-core-regulator;
576*4882a593Smuzhiyun				};
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun				vdd_cpu: sm1 {
579*4882a593Smuzhiyun					regulator-name = "vdd_sm1,vdd_cpu";
580*4882a593Smuzhiyun					regulator-min-microvolt = <750000>;
581*4882a593Smuzhiyun					regulator-max-microvolt = <1125000>;
582*4882a593Smuzhiyun					regulator-coupled-with = <&vdd_core &rtc_vdd>;
583*4882a593Smuzhiyun					regulator-coupled-max-spread = <550000 550000>;
584*4882a593Smuzhiyun					regulator-always-on;
585*4882a593Smuzhiyun					regulator-boot-on;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun					nvidia,tegra-cpu-regulator;
588*4882a593Smuzhiyun				};
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun				sm2_reg: sm2 {
591*4882a593Smuzhiyun					regulator-name = "vdd_sm2,vin_ldo*";
592*4882a593Smuzhiyun					regulator-min-microvolt = <3700000>;
593*4882a593Smuzhiyun					regulator-max-microvolt = <3700000>;
594*4882a593Smuzhiyun					regulator-always-on;
595*4882a593Smuzhiyun				};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun				/* LDO0 is not connected to anything */
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun				ldo1 {
600*4882a593Smuzhiyun					regulator-name = "vdd_ldo1,avdd_pll*";
601*4882a593Smuzhiyun					regulator-min-microvolt = <1100000>;
602*4882a593Smuzhiyun					regulator-max-microvolt = <1100000>;
603*4882a593Smuzhiyun					regulator-always-on;
604*4882a593Smuzhiyun					regulator-boot-on;
605*4882a593Smuzhiyun				};
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun				rtc_vdd: ldo2 {
608*4882a593Smuzhiyun					regulator-name = "vdd_ldo2,vdd_rtc";
609*4882a593Smuzhiyun					regulator-min-microvolt = <1200000>;
610*4882a593Smuzhiyun					regulator-max-microvolt = <1300000>;
611*4882a593Smuzhiyun					regulator-coupled-with = <&vdd_core &vdd_cpu>;
612*4882a593Smuzhiyun					regulator-coupled-max-spread = <170000 550000>;
613*4882a593Smuzhiyun					regulator-always-on;
614*4882a593Smuzhiyun					regulator-boot-on;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun					nvidia,tegra-rtc-regulator;
617*4882a593Smuzhiyun				};
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun				ldo3 {
620*4882a593Smuzhiyun					regulator-name = "vdd_ldo3,avdd_usb*";
621*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
622*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
623*4882a593Smuzhiyun					regulator-always-on;
624*4882a593Smuzhiyun				};
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun				ldo4 {
627*4882a593Smuzhiyun					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
628*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
629*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
630*4882a593Smuzhiyun					regulator-always-on;
631*4882a593Smuzhiyun					regulator-boot-on;
632*4882a593Smuzhiyun				};
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun				vcore_emmc: ldo5 {
635*4882a593Smuzhiyun					regulator-name = "vdd_ldo5,vcore_mmc";
636*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
637*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
638*4882a593Smuzhiyun					regulator-always-on;
639*4882a593Smuzhiyun				};
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun				avdd_vdac_reg: ldo6 {
642*4882a593Smuzhiyun					regulator-name = "vdd_ldo6,avdd_vdac";
643*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
644*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
645*4882a593Smuzhiyun				};
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun				hdmi_vdd_reg: ldo7 {
648*4882a593Smuzhiyun					regulator-name = "vdd_ldo7,avdd_hdmi";
649*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
650*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
651*4882a593Smuzhiyun				};
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun				hdmi_pll_reg: ldo8 {
654*4882a593Smuzhiyun					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
655*4882a593Smuzhiyun					regulator-min-microvolt = <1800000>;
656*4882a593Smuzhiyun					regulator-max-microvolt = <1800000>;
657*4882a593Smuzhiyun				};
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun				ldo9 {
660*4882a593Smuzhiyun					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
661*4882a593Smuzhiyun					regulator-min-microvolt = <2850000>;
662*4882a593Smuzhiyun					regulator-max-microvolt = <2850000>;
663*4882a593Smuzhiyun					regulator-always-on;
664*4882a593Smuzhiyun					regulator-boot-on;
665*4882a593Smuzhiyun				};
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun				ldo_rtc {
668*4882a593Smuzhiyun					regulator-name = "vdd_rtc_out,vdd_cell";
669*4882a593Smuzhiyun					regulator-min-microvolt = <3300000>;
670*4882a593Smuzhiyun					regulator-max-microvolt = <3300000>;
671*4882a593Smuzhiyun					regulator-always-on;
672*4882a593Smuzhiyun					regulator-boot-on;
673*4882a593Smuzhiyun				};
674*4882a593Smuzhiyun			};
675*4882a593Smuzhiyun		};
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun		nct1008: temperature-sensor@4c {
678*4882a593Smuzhiyun			compatible = "onnn,nct1008";
679*4882a593Smuzhiyun			reg = <0x4c>;
680*4882a593Smuzhiyun			vcc-supply = <&vdd_3v3_sys>;
681*4882a593Smuzhiyun			#thermal-sensor-cells = <1>;
682*4882a593Smuzhiyun		};
683*4882a593Smuzhiyun	};
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun	pmc@7000e400 {
686*4882a593Smuzhiyun		nvidia,invert-interrupt;
687*4882a593Smuzhiyun		nvidia,suspend-mode = <1>;
688*4882a593Smuzhiyun		nvidia,cpu-pwr-good-time = <2000>;
689*4882a593Smuzhiyun		nvidia,cpu-pwr-off-time = <100>;
690*4882a593Smuzhiyun		nvidia,core-pwr-good-time = <3845 3845>;
691*4882a593Smuzhiyun		nvidia,core-pwr-off-time = <458>;
692*4882a593Smuzhiyun		nvidia,sys-clock-req-active-high;
693*4882a593Smuzhiyun	};
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun	usb@c5000000 {
696*4882a593Smuzhiyun		compatible = "nvidia,tegra20-udc";
697*4882a593Smuzhiyun		status = "okay";
698*4882a593Smuzhiyun		dr_mode = "peripheral";
699*4882a593Smuzhiyun	};
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun	usb-phy@c5000000 {
702*4882a593Smuzhiyun		status = "okay";
703*4882a593Smuzhiyun		dr_mode = "peripheral";
704*4882a593Smuzhiyun		nvidia,xcvr-setup-use-fuses;
705*4882a593Smuzhiyun		nvidia,xcvr-lsfslew = <2>;
706*4882a593Smuzhiyun		nvidia,xcvr-lsrslew = <2>;
707*4882a593Smuzhiyun	};
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun	usb@c5008000 {
710*4882a593Smuzhiyun		status = "okay";
711*4882a593Smuzhiyun	};
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun	usb-phy@c5008000 {
714*4882a593Smuzhiyun		status = "okay";
715*4882a593Smuzhiyun		nvidia,xcvr-setup-use-fuses;
716*4882a593Smuzhiyun		nvidia,xcvr-lsfslew = <2>;
717*4882a593Smuzhiyun		nvidia,xcvr-lsrslew = <2>;
718*4882a593Smuzhiyun		vbus-supply = <&vdd_5v0_sys>;
719*4882a593Smuzhiyun	};
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun	brcm_wifi_pwrseq: wifi-pwrseq {
722*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun		clocks = <&rtc_32k_wifi>;
725*4882a593Smuzhiyun		clock-names = "ext_clock";
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun		reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
728*4882a593Smuzhiyun		post-power-on-delay-ms = <300>;
729*4882a593Smuzhiyun		power-off-delay-us = <300>;
730*4882a593Smuzhiyun	};
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun	sdmmc1: mmc@c8000000 {
733*4882a593Smuzhiyun		status = "okay";
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun		#address-cells = <1>;
736*4882a593Smuzhiyun		#size-cells = <0>;
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun		assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
739*4882a593Smuzhiyun		assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
740*4882a593Smuzhiyun		assigned-clock-rates = <50000000>;
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun		max-frequency = <50000000>;
743*4882a593Smuzhiyun		keep-power-in-suspend;
744*4882a593Smuzhiyun		bus-width = <4>;
745*4882a593Smuzhiyun		non-removable;
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun		mmc-pwrseq = <&brcm_wifi_pwrseq>;
748*4882a593Smuzhiyun		vmmc-supply = <&vdd_3v3_sys>;
749*4882a593Smuzhiyun		vqmmc-supply = <&vdd_3v3_sys>;
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun		/* Azurewave AW-NH611 BCM4329 */
752*4882a593Smuzhiyun		wifi@1 {
753*4882a593Smuzhiyun			reg = <1>;
754*4882a593Smuzhiyun			compatible = "brcm,bcm4329-fmac";
755*4882a593Smuzhiyun			interrupt-parent = <&gpio>;
756*4882a593Smuzhiyun			interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
757*4882a593Smuzhiyun			interrupt-names = "host-wake";
758*4882a593Smuzhiyun		};
759*4882a593Smuzhiyun	};
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun	sdmmc3: mmc@c8000400 {
762*4882a593Smuzhiyun		status = "okay";
763*4882a593Smuzhiyun		bus-width = <4>;
764*4882a593Smuzhiyun		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
765*4882a593Smuzhiyun		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
766*4882a593Smuzhiyun		vmmc-supply = <&vdd_3v3_sys>;
767*4882a593Smuzhiyun		vqmmc-supply = <&vdd_3v3_sys>;
768*4882a593Smuzhiyun	};
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun	sdmmc4: mmc@c8000600 {
771*4882a593Smuzhiyun		status = "okay";
772*4882a593Smuzhiyun		bus-width = <8>;
773*4882a593Smuzhiyun		vmmc-supply = <&vcore_emmc>;
774*4882a593Smuzhiyun		vqmmc-supply = <&vdd_3v3_sys>;
775*4882a593Smuzhiyun		non-removable;
776*4882a593Smuzhiyun	};
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun	mains: ac-adapter-detect {
779*4882a593Smuzhiyun		compatible = "gpio-charger";
780*4882a593Smuzhiyun		charger-type = "mains";
781*4882a593Smuzhiyun		gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
782*4882a593Smuzhiyun	};
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun	backlight: backlight {
785*4882a593Smuzhiyun		compatible = "pwm-backlight";
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
788*4882a593Smuzhiyun		power-supply = <&vdd_3v3_sys>;
789*4882a593Smuzhiyun		pwms = <&pwm 2 41667>;
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun		brightness-levels = <7 255>;
792*4882a593Smuzhiyun		num-interpolated-steps = <248>;
793*4882a593Smuzhiyun		default-brightness-level = <20>;
794*4882a593Smuzhiyun	};
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
797*4882a593Smuzhiyun	clk32k_in: clock@0 {
798*4882a593Smuzhiyun		compatible = "fixed-clock";
799*4882a593Smuzhiyun		#clock-cells = <0>;
800*4882a593Smuzhiyun		clock-frequency = <32768>;
801*4882a593Smuzhiyun		clock-output-names = "tps658621-out32k";
802*4882a593Smuzhiyun	};
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun	/*
805*4882a593Smuzhiyun	 * This standalone onboard fixed-clock always-ON 32KHz
806*4882a593Smuzhiyun	 * oscillator is used as a reference clock-source by the
807*4882a593Smuzhiyun	 * Azurewave WiFi/BT module.
808*4882a593Smuzhiyun	 */
809*4882a593Smuzhiyun	rtc_32k_wifi: clock@1 {
810*4882a593Smuzhiyun		compatible = "fixed-clock";
811*4882a593Smuzhiyun		#clock-cells = <0>;
812*4882a593Smuzhiyun		clock-frequency = <32768>;
813*4882a593Smuzhiyun		clock-output-names = "kk3270032";
814*4882a593Smuzhiyun	};
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun	cpus {
817*4882a593Smuzhiyun		cpu0: cpu@0 {
818*4882a593Smuzhiyun			cpu-supply = <&vdd_cpu>;
819*4882a593Smuzhiyun			operating-points-v2 = <&cpu0_opp_table>;
820*4882a593Smuzhiyun			#cooling-cells = <2>;
821*4882a593Smuzhiyun		};
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun		cpu@1 {
824*4882a593Smuzhiyun			cpu-supply = <&vdd_cpu>;
825*4882a593Smuzhiyun			operating-points-v2 = <&cpu0_opp_table>;
826*4882a593Smuzhiyun		};
827*4882a593Smuzhiyun	};
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun	display-panel {
830*4882a593Smuzhiyun		compatible = "auo,b101ew05", "panel-lvds";
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun		ddc-i2c-bus = <&panel_ddc>;
833*4882a593Smuzhiyun		power-supply = <&vdd_pnl>;
834*4882a593Smuzhiyun		backlight = <&backlight>;
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun		width-mm = <218>;
837*4882a593Smuzhiyun		height-mm = <135>;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun		data-mapping = "jeida-18";
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun		panel-timing {
842*4882a593Smuzhiyun			clock-frequency = <71200000>;
843*4882a593Smuzhiyun			hactive = <1280>;
844*4882a593Smuzhiyun			vactive = <800>;
845*4882a593Smuzhiyun			hfront-porch = <8>;
846*4882a593Smuzhiyun			hback-porch = <18>;
847*4882a593Smuzhiyun			hsync-len = <184>;
848*4882a593Smuzhiyun			vsync-len = <3>;
849*4882a593Smuzhiyun			vfront-porch = <4>;
850*4882a593Smuzhiyun			vback-porch = <8>;
851*4882a593Smuzhiyun		};
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun		port {
854*4882a593Smuzhiyun			panel_input: endpoint {
855*4882a593Smuzhiyun				remote-endpoint = <&lvds_encoder_output>;
856*4882a593Smuzhiyun			};
857*4882a593Smuzhiyun		};
858*4882a593Smuzhiyun	};
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun	gpio-keys {
861*4882a593Smuzhiyun		compatible = "gpio-keys";
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun		power {
864*4882a593Smuzhiyun			label = "Power";
865*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
866*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
867*4882a593Smuzhiyun			debounce-interval = <10>;
868*4882a593Smuzhiyun			wakeup-event-action = <EV_ACT_ASSERTED>;
869*4882a593Smuzhiyun			wakeup-source;
870*4882a593Smuzhiyun		};
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun		rotation-lock {
873*4882a593Smuzhiyun			label = "Rotate-lock";
874*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
875*4882a593Smuzhiyun			linux,code = <SW_ROTATE_LOCK>;
876*4882a593Smuzhiyun			linux,input-type = <EV_SW>;
877*4882a593Smuzhiyun			debounce-interval = <10>;
878*4882a593Smuzhiyun		};
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun		volume-up {
881*4882a593Smuzhiyun			label = "Volume Up";
882*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
883*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
884*4882a593Smuzhiyun			debounce-interval = <10>;
885*4882a593Smuzhiyun			wakeup-event-action = <EV_ACT_ASSERTED>;
886*4882a593Smuzhiyun			wakeup-source;
887*4882a593Smuzhiyun		};
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun		volume-down {
890*4882a593Smuzhiyun			label = "Volume Down";
891*4882a593Smuzhiyun			gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
892*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
893*4882a593Smuzhiyun			debounce-interval = <10>;
894*4882a593Smuzhiyun			wakeup-event-action = <EV_ACT_ASSERTED>;
895*4882a593Smuzhiyun			wakeup-source;
896*4882a593Smuzhiyun		};
897*4882a593Smuzhiyun	};
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun	haptic-feedback {
900*4882a593Smuzhiyun		compatible = "gpio-vibrator";
901*4882a593Smuzhiyun		enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
902*4882a593Smuzhiyun		vcc-supply = <&vdd_3v3_sys>;
903*4882a593Smuzhiyun	};
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun	lvds-encoder {
906*4882a593Smuzhiyun		compatible = "ti,sn75lvds83", "lvds-encoder";
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun		powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun		ports {
911*4882a593Smuzhiyun			#address-cells = <1>;
912*4882a593Smuzhiyun			#size-cells = <0>;
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun			port@0 {
915*4882a593Smuzhiyun				reg = <0>;
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun				lvds_encoder_input: endpoint {
918*4882a593Smuzhiyun					remote-endpoint = <&lcd_output>;
919*4882a593Smuzhiyun				};
920*4882a593Smuzhiyun			};
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun			port@1 {
923*4882a593Smuzhiyun				reg = <1>;
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun				lvds_encoder_output: endpoint {
926*4882a593Smuzhiyun					remote-endpoint = <&panel_input>;
927*4882a593Smuzhiyun				};
928*4882a593Smuzhiyun			};
929*4882a593Smuzhiyun		};
930*4882a593Smuzhiyun	};
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun	vdd_5v0_sys: regulator@0 {
933*4882a593Smuzhiyun		compatible = "regulator-fixed";
934*4882a593Smuzhiyun		regulator-name = "vdd_5v0";
935*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
936*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
937*4882a593Smuzhiyun		regulator-always-on;
938*4882a593Smuzhiyun	};
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun	vdd_3v3_sys: regulator@1 {
941*4882a593Smuzhiyun		compatible = "regulator-fixed";
942*4882a593Smuzhiyun		regulator-name = "vdd_3v3_vs";
943*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
944*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
945*4882a593Smuzhiyun		regulator-always-on;
946*4882a593Smuzhiyun		vin-supply = <&vdd_5v0_sys>;
947*4882a593Smuzhiyun	};
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun	vdd_1v8_sys: regulator@2 {
950*4882a593Smuzhiyun		compatible = "regulator-fixed";
951*4882a593Smuzhiyun		regulator-name = "vdd_1v8_vs";
952*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
953*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
954*4882a593Smuzhiyun		regulator-always-on;
955*4882a593Smuzhiyun		vin-supply = <&vdd_5v0_sys>;
956*4882a593Smuzhiyun	};
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun	vdd_pnl: regulator@3 {
959*4882a593Smuzhiyun		compatible = "regulator-fixed";
960*4882a593Smuzhiyun		regulator-name = "vdd_panel";
961*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
962*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
963*4882a593Smuzhiyun		regulator-enable-ramp-delay = <300000>;
964*4882a593Smuzhiyun		gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
965*4882a593Smuzhiyun		enable-active-high;
966*4882a593Smuzhiyun		vin-supply = <&vdd_5v0_sys>;
967*4882a593Smuzhiyun	};
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun	sound {
970*4882a593Smuzhiyun		compatible = "nvidia,tegra-audio-wm8903-picasso",
971*4882a593Smuzhiyun			     "nvidia,tegra-audio-wm8903";
972*4882a593Smuzhiyun		nvidia,model = "Acer Iconia Tab A500 WM8903";
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun		nvidia,audio-routing =
975*4882a593Smuzhiyun			"Headphone Jack", "HPOUTR",
976*4882a593Smuzhiyun			"Headphone Jack", "HPOUTL",
977*4882a593Smuzhiyun			"Int Spk", "LINEOUTL",
978*4882a593Smuzhiyun			"Int Spk", "LINEOUTR",
979*4882a593Smuzhiyun			"Mic Jack", "MICBIAS",
980*4882a593Smuzhiyun			"IN2L", "Mic Jack",
981*4882a593Smuzhiyun			"IN2R", "Mic Jack",
982*4882a593Smuzhiyun			"IN1L", "Int Mic",
983*4882a593Smuzhiyun			"IN1R", "Int Mic";
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun		nvidia,i2s-controller = <&tegra_i2s1>;
986*4882a593Smuzhiyun		nvidia,audio-codec = <&wm8903>;
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
989*4882a593Smuzhiyun		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
990*4882a593Smuzhiyun		nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
991*4882a593Smuzhiyun		nvidia,headset;
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
994*4882a593Smuzhiyun			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
995*4882a593Smuzhiyun			 <&tegra_car TEGRA20_CLK_CDEV1>;
996*4882a593Smuzhiyun		clock-names = "pll_a", "pll_a_out0", "mclk";
997*4882a593Smuzhiyun	};
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun	thermal-zones {
1000*4882a593Smuzhiyun		nct1008-local {
1001*4882a593Smuzhiyun			polling-delay-passive = <1000>; /* milliseconds */
1002*4882a593Smuzhiyun			polling-delay = <0>; /* milliseconds */
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun			thermal-sensors = <&nct1008 0>;
1005*4882a593Smuzhiyun		};
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun		nct1008-remote {
1008*4882a593Smuzhiyun			polling-delay-passive = <1000>; /* milliseconds */
1009*4882a593Smuzhiyun			polling-delay = <5000>; /* milliseconds */
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun			thermal-sensors = <&nct1008 1>;
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun			trips {
1014*4882a593Smuzhiyun				trip0: cpu-alert0 {
1015*4882a593Smuzhiyun					/* start throttling at 50C */
1016*4882a593Smuzhiyun					temperature = <50000>;
1017*4882a593Smuzhiyun					hysteresis = <3000>;
1018*4882a593Smuzhiyun					type = "passive";
1019*4882a593Smuzhiyun				};
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun				trip1: cpu-crit {
1022*4882a593Smuzhiyun					/* shut down at 60C */
1023*4882a593Smuzhiyun					temperature = <60000>;
1024*4882a593Smuzhiyun					hysteresis = <2000>;
1025*4882a593Smuzhiyun					type = "critical";
1026*4882a593Smuzhiyun				};
1027*4882a593Smuzhiyun			};
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun			cooling-maps {
1030*4882a593Smuzhiyun				map0 {
1031*4882a593Smuzhiyun					trip = <&trip0>;
1032*4882a593Smuzhiyun					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1033*4882a593Smuzhiyun				};
1034*4882a593Smuzhiyun			};
1035*4882a593Smuzhiyun		};
1036*4882a593Smuzhiyun	};
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun	memory-controller@7000f400 {
1039*4882a593Smuzhiyun		nvidia,use-ram-code;
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun		emc-tables@0 {
1042*4882a593Smuzhiyun			nvidia,ram-code = <0>; /* elpida-8gb */
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun			#address-cells = <1>;
1045*4882a593Smuzhiyun			#size-cells = <0>;
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun			emc-table@25000 {
1048*4882a593Smuzhiyun				reg = <25000>;
1049*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1050*4882a593Smuzhiyun				clock-frequency = <25000>;
1051*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000002 0x00000006
1052*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000006 0x00000004
1053*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1054*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000004
1055*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000004d
1056*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1057*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000004
1058*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1059*4882a593Smuzhiyun					0x00000002 0x00000068 0x00000000 0x00000003
1060*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1061*4882a593Smuzhiyun					0x00070000 0x00000000 0x00000000 0x00000003
1062*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1063*4882a593Smuzhiyun			};
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun			emc-table@50000 {
1066*4882a593Smuzhiyun				reg = <50000>;
1067*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1068*4882a593Smuzhiyun				clock-frequency = <50000>;
1069*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000003 0x00000007
1070*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000006 0x00000004
1071*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1072*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1073*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000009f
1074*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1075*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000007
1076*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1077*4882a593Smuzhiyun					0x00000002 0x000000d0 0x00000000 0x00000000
1078*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1079*4882a593Smuzhiyun					0x00070000 0x00000000 0x00000000 0x00000005
1080*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1081*4882a593Smuzhiyun			};
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun			emc-table@75000 {
1084*4882a593Smuzhiyun				reg = <75000>;
1085*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1086*4882a593Smuzhiyun				clock-frequency = <75000>;
1087*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000005 0x0000000a
1088*4882a593Smuzhiyun					0x00000004 0x00000003 0x00000006 0x00000004
1089*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1090*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1091*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x000000ff
1092*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1093*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x0000000b
1094*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1095*4882a593Smuzhiyun					0x00000002 0x00000138 0x00000000 0x00000000
1096*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1097*4882a593Smuzhiyun					0x00070000 0x00000000 0x00000000 0x00000007
1098*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1099*4882a593Smuzhiyun			};
1100*4882a593Smuzhiyun
1101*4882a593Smuzhiyun			emc-table@150000 {
1102*4882a593Smuzhiyun				reg = <150000>;
1103*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1104*4882a593Smuzhiyun				clock-frequency = <150000>;
1105*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000009 0x00000014
1106*4882a593Smuzhiyun					0x00000007 0x00000003 0x00000006 0x00000004
1107*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1108*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1109*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000021f
1110*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1111*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000015
1112*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1113*4882a593Smuzhiyun					0x00000002 0x00000270 0x00000000 0x00000001
1114*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa07c04ae
1115*4882a593Smuzhiyun					0x007dd510 0x00000000 0x00000000 0x0000000e
1116*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1117*4882a593Smuzhiyun			};
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun			emc-table@300000 {
1120*4882a593Smuzhiyun				reg = <300000>;
1121*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1122*4882a593Smuzhiyun				clock-frequency = <300000>;
1123*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000012 0x00000027
1124*4882a593Smuzhiyun					0x0000000d 0x00000006 0x00000007 0x00000005
1125*4882a593Smuzhiyun					0x00000003 0x00000009 0x00000006 0x00000006
1126*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000002 0x00000006
1127*4882a593Smuzhiyun					0x00000003 0x00000009 0x0000000c 0x0000045f
1128*4882a593Smuzhiyun					0x00000000 0x00000004 0x00000004 0x00000006
1129*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000e 0x0000002a
1130*4882a593Smuzhiyun					0x00000003 0x0000000f 0x00000007 0x00000005
1131*4882a593Smuzhiyun					0x00000002 0x000004e1 0x00000005 0x00000002
1132*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xe059048b
1133*4882a593Smuzhiyun					0x007e1510 0x00000000 0x00000000 0x0000001b
1134*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1135*4882a593Smuzhiyun			};
1136*4882a593Smuzhiyun		};
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun		emc-tables@1 {
1139*4882a593Smuzhiyun			nvidia,ram-code = <1>; /* elpida-4gb */
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun			#address-cells = <1>;
1142*4882a593Smuzhiyun			#size-cells = <0>;
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun			emc-table@25000 {
1145*4882a593Smuzhiyun				reg = <25000>;
1146*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1147*4882a593Smuzhiyun				clock-frequency = <25000>;
1148*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000002 0x00000006
1149*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000006 0x00000004
1150*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1151*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000004
1152*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000004d
1153*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1154*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000004
1155*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1156*4882a593Smuzhiyun					0x00000002 0x00000068 0x00000000 0x00000003
1157*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1158*4882a593Smuzhiyun					0x0007c000 0x00000000 0x00000000 0x00000003
1159*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1160*4882a593Smuzhiyun			};
1161*4882a593Smuzhiyun
1162*4882a593Smuzhiyun			emc-table@50000 {
1163*4882a593Smuzhiyun				reg = <50000>;
1164*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1165*4882a593Smuzhiyun				clock-frequency = <50000>;
1166*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000003 0x00000007
1167*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000006 0x00000004
1168*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1169*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1170*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000009f
1171*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1172*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000007
1173*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1174*4882a593Smuzhiyun					0x00000002 0x000000d0 0x00000000 0x00000000
1175*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1176*4882a593Smuzhiyun					0x0007c000 0x00000000 0x00000000 0x00000005
1177*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1178*4882a593Smuzhiyun			};
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun			emc-table@75000 {
1181*4882a593Smuzhiyun				reg = <75000>;
1182*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1183*4882a593Smuzhiyun				clock-frequency = <75000>;
1184*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000005 0x0000000a
1185*4882a593Smuzhiyun					0x00000004 0x00000003 0x00000006 0x00000004
1186*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1187*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1188*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x000000ff
1189*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1190*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x0000000b
1191*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1192*4882a593Smuzhiyun					0x00000002 0x00000138 0x00000000 0x00000000
1193*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1194*4882a593Smuzhiyun					0x0007c000 0x00000000 0x00000000 0x00000007
1195*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1196*4882a593Smuzhiyun			};
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun			emc-table@150000 {
1199*4882a593Smuzhiyun				reg = <150000>;
1200*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1201*4882a593Smuzhiyun				clock-frequency = <150000>;
1202*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000009 0x00000014
1203*4882a593Smuzhiyun					0x00000007 0x00000003 0x00000006 0x00000004
1204*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1205*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1206*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000021f
1207*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1208*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000015
1209*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1210*4882a593Smuzhiyun					0x00000002 0x00000270 0x00000000 0x00000001
1211*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa07c04ae
1212*4882a593Smuzhiyun					0x007e4010 0x00000000 0x00000000 0x0000000e
1213*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1214*4882a593Smuzhiyun			};
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun			emc-table@300000 {
1217*4882a593Smuzhiyun				reg = <300000>;
1218*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1219*4882a593Smuzhiyun				clock-frequency = <300000>;
1220*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000012 0x00000027
1221*4882a593Smuzhiyun					0x0000000d 0x00000006 0x00000007 0x00000005
1222*4882a593Smuzhiyun					0x00000003 0x00000009 0x00000006 0x00000006
1223*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000002 0x00000006
1224*4882a593Smuzhiyun					0x00000003 0x00000009 0x0000000c 0x0000045f
1225*4882a593Smuzhiyun					0x00000000 0x00000004 0x00000004 0x00000006
1226*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000e 0x0000002a
1227*4882a593Smuzhiyun					0x00000003 0x0000000f 0x00000007 0x00000005
1228*4882a593Smuzhiyun					0x00000002 0x000004e1 0x00000005 0x00000002
1229*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xe059048b
1230*4882a593Smuzhiyun					0x007e0010 0x00000000 0x00000000 0x0000001b
1231*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1232*4882a593Smuzhiyun			};
1233*4882a593Smuzhiyun		};
1234*4882a593Smuzhiyun
1235*4882a593Smuzhiyun		emc-tables@2 {
1236*4882a593Smuzhiyun			nvidia,ram-code = <2>; /* hynix-8gb */
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun			#address-cells = <1>;
1239*4882a593Smuzhiyun			#size-cells = <0>;
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun			emc-table@25000 {
1242*4882a593Smuzhiyun				reg = <25000>;
1243*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1244*4882a593Smuzhiyun				clock-frequency = <25000>;
1245*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000002 0x00000006
1246*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000006 0x00000004
1247*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1248*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000004
1249*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000004d
1250*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1251*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000004
1252*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1253*4882a593Smuzhiyun					0x00000002 0x00000068 0x00000000 0x00000003
1254*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1255*4882a593Smuzhiyun					0x00070000 0x00000000 0x00000000 0x00000003
1256*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1257*4882a593Smuzhiyun			};
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun			emc-table@50000 {
1260*4882a593Smuzhiyun				reg = <50000>;
1261*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1262*4882a593Smuzhiyun				clock-frequency = <50000>;
1263*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000003 0x00000007
1264*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000006 0x00000004
1265*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1266*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1267*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000009f
1268*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1269*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000007
1270*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1271*4882a593Smuzhiyun					0x00000002 0x000000d0 0x00000000 0x00000000
1272*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1273*4882a593Smuzhiyun					0x00070000 0x00000000 0x00000000 0x00000005
1274*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1275*4882a593Smuzhiyun			};
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun			emc-table@75000 {
1278*4882a593Smuzhiyun				reg = <75000>;
1279*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1280*4882a593Smuzhiyun				clock-frequency = <75000>;
1281*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000005 0x0000000a
1282*4882a593Smuzhiyun					0x00000004 0x00000003 0x00000006 0x00000004
1283*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1284*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1285*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x000000ff
1286*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1287*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x0000000b
1288*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1289*4882a593Smuzhiyun					0x00000002 0x00000138 0x00000000 0x00000000
1290*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1291*4882a593Smuzhiyun					0x00070000 0x00000000 0x00000000 0x00000007
1292*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1293*4882a593Smuzhiyun			};
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun			emc-table@150000 {
1296*4882a593Smuzhiyun				reg = <150000>;
1297*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1298*4882a593Smuzhiyun				clock-frequency = <150000>;
1299*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000009 0x00000014
1300*4882a593Smuzhiyun					0x00000007 0x00000003 0x00000006 0x00000004
1301*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1302*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1303*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000021f
1304*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1305*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000015
1306*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1307*4882a593Smuzhiyun					0x00000002 0x00000270 0x00000000 0x00000001
1308*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa07c04ae
1309*4882a593Smuzhiyun					0x007dd010 0x00000000 0x00000000 0x0000000e
1310*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1311*4882a593Smuzhiyun			};
1312*4882a593Smuzhiyun
1313*4882a593Smuzhiyun			emc-table@300000 {
1314*4882a593Smuzhiyun				reg = <300000>;
1315*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1316*4882a593Smuzhiyun				clock-frequency = <300000>;
1317*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000012 0x00000027
1318*4882a593Smuzhiyun					0x0000000d 0x00000006 0x00000007 0x00000005
1319*4882a593Smuzhiyun					0x00000003 0x00000009 0x00000006 0x00000006
1320*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000002 0x00000006
1321*4882a593Smuzhiyun					0x00000003 0x00000009 0x0000000c 0x0000045f
1322*4882a593Smuzhiyun					0x00000000 0x00000004 0x00000004 0x00000006
1323*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000e 0x0000002a
1324*4882a593Smuzhiyun					0x00000003 0x0000000f 0x00000007 0x00000005
1325*4882a593Smuzhiyun					0x00000002 0x000004e1 0x00000005 0x00000002
1326*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xe059048b
1327*4882a593Smuzhiyun					0x007e2010 0x00000000 0x00000000 0x0000001b
1328*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1329*4882a593Smuzhiyun			};
1330*4882a593Smuzhiyun		};
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun		emc-tables@3 {
1333*4882a593Smuzhiyun			nvidia,ram-code = <3>; /* hynix-4gb */
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun			#address-cells = <1>;
1336*4882a593Smuzhiyun			#size-cells = <0>;
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun			emc-table@25000 {
1339*4882a593Smuzhiyun				reg = <25000>;
1340*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1341*4882a593Smuzhiyun				clock-frequency = <25000>;
1342*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000002 0x00000006
1343*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000006 0x00000004
1344*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1345*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000004
1346*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000004d
1347*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1348*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000004
1349*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1350*4882a593Smuzhiyun					0x00000002 0x00000068 0x00000000 0x00000003
1351*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1352*4882a593Smuzhiyun					0x0007c000 0x00000000 0x00000000 0x00000003
1353*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1354*4882a593Smuzhiyun			};
1355*4882a593Smuzhiyun
1356*4882a593Smuzhiyun			emc-table@50000 {
1357*4882a593Smuzhiyun				reg = <50000>;
1358*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1359*4882a593Smuzhiyun				clock-frequency = <50000>;
1360*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000003 0x00000007
1361*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000006 0x00000004
1362*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1363*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1364*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000009f
1365*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1366*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000007
1367*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1368*4882a593Smuzhiyun					0x00000002 0x000000d0 0x00000000 0x00000000
1369*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1370*4882a593Smuzhiyun					0x0007c000 0x00078000 0x00000000 0x00000005
1371*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1372*4882a593Smuzhiyun			};
1373*4882a593Smuzhiyun
1374*4882a593Smuzhiyun			emc-table@75000 {
1375*4882a593Smuzhiyun				reg = <75000>;
1376*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1377*4882a593Smuzhiyun				clock-frequency = <75000>;
1378*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000005 0x0000000a
1379*4882a593Smuzhiyun					0x00000004 0x00000003 0x00000006 0x00000004
1380*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1381*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1382*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x000000ff
1383*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1384*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x0000000b
1385*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1386*4882a593Smuzhiyun					0x00000002 0x00000138 0x00000000 0x00000000
1387*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1388*4882a593Smuzhiyun					0x0007c000 0x00000000 0x00000000 0x00000007
1389*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1390*4882a593Smuzhiyun			};
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun			emc-table@150000 {
1393*4882a593Smuzhiyun				reg = <150000>;
1394*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1395*4882a593Smuzhiyun				clock-frequency = <150000>;
1396*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000009 0x00000014
1397*4882a593Smuzhiyun					0x00000007 0x00000003 0x00000006 0x00000004
1398*4882a593Smuzhiyun					0x00000002 0x00000009 0x00000003 0x00000003
1399*4882a593Smuzhiyun					0x00000002 0x00000002 0x00000002 0x00000005
1400*4882a593Smuzhiyun					0x00000003 0x00000008 0x0000000b 0x0000021f
1401*4882a593Smuzhiyun					0x00000000 0x00000003 0x00000003 0x00000003
1402*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000a 0x00000015
1403*4882a593Smuzhiyun					0x00000003 0x00000008 0x00000004 0x00000006
1404*4882a593Smuzhiyun					0x00000002 0x00000270 0x00000000 0x00000001
1405*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xa07c04ae
1406*4882a593Smuzhiyun					0x007e4010 0x00000000 0x00000000 0x0000000e
1407*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1408*4882a593Smuzhiyun			};
1409*4882a593Smuzhiyun
1410*4882a593Smuzhiyun			emc-table@300000 {
1411*4882a593Smuzhiyun				reg = <300000>;
1412*4882a593Smuzhiyun				compatible = "nvidia,tegra20-emc-table";
1413*4882a593Smuzhiyun				clock-frequency = <300000>;
1414*4882a593Smuzhiyun				nvidia,emc-registers = <0x00000012 0x00000027
1415*4882a593Smuzhiyun					0x0000000d 0x00000006 0x00000007 0x00000005
1416*4882a593Smuzhiyun					0x00000003 0x00000009 0x00000006 0x00000006
1417*4882a593Smuzhiyun					0x00000003 0x00000003 0x00000002 0x00000006
1418*4882a593Smuzhiyun					0x00000003 0x00000009 0x0000000c 0x0000045f
1419*4882a593Smuzhiyun					0x00000000 0x00000004 0x00000004 0x00000006
1420*4882a593Smuzhiyun					0x00000008 0x00000001 0x0000000e 0x0000002a
1421*4882a593Smuzhiyun					0x00000003 0x0000000f 0x00000007 0x00000005
1422*4882a593Smuzhiyun					0x00000002 0x000004e1 0x00000005 0x00000002
1423*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000282 0xe059048b
1424*4882a593Smuzhiyun					0x007e0010 0x00000000 0x00000000 0x0000001b
1425*4882a593Smuzhiyun					0x00000000 0x00000000 0x00000000 0x00000000>;
1426*4882a593Smuzhiyun			};
1427*4882a593Smuzhiyun		};
1428*4882a593Smuzhiyun	};
1429*4882a593Smuzhiyun};
1430