1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2015 Altera Corporation <www.altera.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun#include "socfpga_arria10.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun model = "Altera SOCFPGA Arria 10"; 9*4882a593Smuzhiyun compatible = "altr,socfpga-arria10", "altr,socfpga"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun aliases { 12*4882a593Smuzhiyun ethernet0 = &gmac0; 13*4882a593Smuzhiyun serial0 = &uart1; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun bootargs = "earlyprintk"; 18*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory@0 { 22*4882a593Smuzhiyun name = "memory"; 23*4882a593Smuzhiyun device_type = "memory"; 24*4882a593Smuzhiyun reg = <0x0 0x40000000>; /* 1GB */ 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun a10leds { 28*4882a593Smuzhiyun compatible = "gpio-leds"; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun a10sr_led0 { 31*4882a593Smuzhiyun label = "a10sr-led0"; 32*4882a593Smuzhiyun gpios = <&a10sr_gpio 0 1>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun a10sr_led1 { 36*4882a593Smuzhiyun label = "a10sr-led1"; 37*4882a593Smuzhiyun gpios = <&a10sr_gpio 1 1>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun a10sr_led2 { 41*4882a593Smuzhiyun label = "a10sr-led2"; 42*4882a593Smuzhiyun gpios = <&a10sr_gpio 2 1>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun a10sr_led3 { 46*4882a593Smuzhiyun label = "a10sr-led3"; 47*4882a593Smuzhiyun gpios = <&a10sr_gpio 3 1>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun ref_033v: 033-v-ref { 52*4882a593Smuzhiyun compatible = "regulator-fixed"; 53*4882a593Smuzhiyun regulator-name = "0.33V"; 54*4882a593Smuzhiyun regulator-min-microvolt = <330000>; 55*4882a593Smuzhiyun regulator-max-microvolt = <330000>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun soc { 59*4882a593Smuzhiyun clkmgr@ffd04000 { 60*4882a593Smuzhiyun clocks { 61*4882a593Smuzhiyun osc1 { 62*4882a593Smuzhiyun clock-frequency = <25000000>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun&gmac0 { 70*4882a593Smuzhiyun phy-mode = "rgmii"; 71*4882a593Smuzhiyun phy-addr = <0xffffffff>; /* probe for phy addr */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * These skews assume the user's FPGA design is adding 600ps of delay 75*4882a593Smuzhiyun * for TX_CLK on Arria 10. 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * All skews are offset since hardware skew values for the ksz9031 78*4882a593Smuzhiyun * range from a negative skew to a positive skew. 79*4882a593Smuzhiyun * See the micrel-ksz90x1.txt Documentation file for details. 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun txd0-skew-ps = <0>; /* -420ps */ 82*4882a593Smuzhiyun txd1-skew-ps = <0>; /* -420ps */ 83*4882a593Smuzhiyun txd2-skew-ps = <0>; /* -420ps */ 84*4882a593Smuzhiyun txd3-skew-ps = <0>; /* -420ps */ 85*4882a593Smuzhiyun rxd0-skew-ps = <420>; /* 0ps */ 86*4882a593Smuzhiyun rxd1-skew-ps = <420>; /* 0ps */ 87*4882a593Smuzhiyun rxd2-skew-ps = <420>; /* 0ps */ 88*4882a593Smuzhiyun rxd3-skew-ps = <420>; /* 0ps */ 89*4882a593Smuzhiyun txen-skew-ps = <0>; /* -420ps */ 90*4882a593Smuzhiyun txc-skew-ps = <1860>; /* 960ps */ 91*4882a593Smuzhiyun rxdv-skew-ps = <420>; /* 0ps */ 92*4882a593Smuzhiyun rxc-skew-ps = <1680>; /* 780ps */ 93*4882a593Smuzhiyun max-frame-size = <3800>; 94*4882a593Smuzhiyun status = "okay"; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun&gpio1 { 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&spi1 { 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun resource-manager@0 { 105*4882a593Smuzhiyun compatible = "altr,a10sr"; 106*4882a593Smuzhiyun reg = <0>; 107*4882a593Smuzhiyun spi-max-frequency = <100000>; 108*4882a593Smuzhiyun /* low-level active IRQ at GPIO1_5 */ 109*4882a593Smuzhiyun interrupt-parent = <&portb>; 110*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 111*4882a593Smuzhiyun interrupt-controller; 112*4882a593Smuzhiyun #interrupt-cells = <2>; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun a10sr_gpio: gpio-controller { 115*4882a593Smuzhiyun compatible = "altr,a10sr-gpio"; 116*4882a593Smuzhiyun gpio-controller; 117*4882a593Smuzhiyun #gpio-cells = <2>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun a10sr_rst: reset-controller { 121*4882a593Smuzhiyun compatible = "altr,a10sr-reset"; 122*4882a593Smuzhiyun #reset-cells = <1>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun}; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun&i2c1 { 128*4882a593Smuzhiyun status = "okay"; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* 131*4882a593Smuzhiyun * adjust the falling times to decrease the i2c frequency to 50Khz 132*4882a593Smuzhiyun * because the LCD module does not work at the standard 100Khz 133*4882a593Smuzhiyun */ 134*4882a593Smuzhiyun clock-frequency = <100000>; 135*4882a593Smuzhiyun i2c-sda-falling-time-ns = <6000>; 136*4882a593Smuzhiyun i2c-scl-falling-time-ns = <6000>; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun adc@14 { 139*4882a593Smuzhiyun compatible = "lltc,ltc2497"; 140*4882a593Smuzhiyun reg = <0x14>; 141*4882a593Smuzhiyun vref-supply = <&ref_033v>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun adc@16 { 145*4882a593Smuzhiyun compatible = "lltc,ltc2497"; 146*4882a593Smuzhiyun reg = <0x16>; 147*4882a593Smuzhiyun vref-supply = <&ref_033v>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun eeprom@51 { 151*4882a593Smuzhiyun compatible = "atmel,24c32"; 152*4882a593Smuzhiyun reg = <0x51>; 153*4882a593Smuzhiyun pagesize = <32>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun rtc@68 { 157*4882a593Smuzhiyun compatible = "dallas,ds1339"; 158*4882a593Smuzhiyun reg = <0x68>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun ltc@5c { 162*4882a593Smuzhiyun compatible = "ltc2977"; 163*4882a593Smuzhiyun reg = <0x5c>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun temp@4c { 167*4882a593Smuzhiyun compatible = "maxim,max1619"; 168*4882a593Smuzhiyun reg = <0x4c>; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun}; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun&uart1 { 173*4882a593Smuzhiyun status = "okay"; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&usb0 { 177*4882a593Smuzhiyun status = "okay"; 178*4882a593Smuzhiyun disable-over-current; 179*4882a593Smuzhiyun}; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun&watchdog1 { 182*4882a593Smuzhiyun status = "okay"; 183*4882a593Smuzhiyun}; 184