1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with 4*4882a593Smuzhiyun * CAN support 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h> 10*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun ahb { 14*4882a593Smuzhiyun apb { 15*4882a593Smuzhiyun pinctrl@fffff200 { 16*4882a593Smuzhiyun can0 { 17*4882a593Smuzhiyun pinctrl_can0_rx_tx: can0_rx_tx { 18*4882a593Smuzhiyun atmel,pins = 19*4882a593Smuzhiyun <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ 20*4882a593Smuzhiyun AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun can1 { 25*4882a593Smuzhiyun pinctrl_can1_rx_tx: can1_rx_tx { 26*4882a593Smuzhiyun atmel,pins = 27*4882a593Smuzhiyun <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ 28*4882a593Smuzhiyun AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun can0: can@f000c000 { 35*4882a593Smuzhiyun compatible = "atmel,at91sam9x5-can"; 36*4882a593Smuzhiyun reg = <0xf000c000 0x300>; 37*4882a593Smuzhiyun interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; 38*4882a593Smuzhiyun pinctrl-names = "default"; 39*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can0_rx_tx>; 40*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 41*4882a593Smuzhiyun clock-names = "can_clk"; 42*4882a593Smuzhiyun status = "disabled"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun can1: can@f8010000 { 46*4882a593Smuzhiyun compatible = "atmel,at91sam9x5-can"; 47*4882a593Smuzhiyun reg = <0xf8010000 0x300>; 48*4882a593Smuzhiyun interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; 49*4882a593Smuzhiyun pinctrl-names = "default"; 50*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can1_rx_tx>; 51*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 52*4882a593Smuzhiyun clock-names = "can_clk"; 53*4882a593Smuzhiyun status = "disabled"; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun}; 58