1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "rv1126-bat-ipc-v10.dts" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Rockchip RV1126 BAT IPC 4K V10 Board"; 11*4882a593Smuzhiyun compatible = "rockchip,rv1126-bat-ipc-4k-v10", "rockchip,rv1126"; 12*4882a593Smuzhiyun}; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun&csi_dphy0 { 15*4882a593Smuzhiyun status = "okay"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun ports { 18*4882a593Smuzhiyun #address-cells = <1>; 19*4882a593Smuzhiyun #size-cells = <0>; 20*4882a593Smuzhiyun port@0 { 21*4882a593Smuzhiyun reg = <0>; 22*4882a593Smuzhiyun #address-cells = <1>; 23*4882a593Smuzhiyun #size-cells = <0>; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 26*4882a593Smuzhiyun reg = <1>; 27*4882a593Smuzhiyun remote-endpoint = <&ucam_out0>; 28*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun port@1 { 32*4882a593Smuzhiyun reg = <1>; 33*4882a593Smuzhiyun #address-cells = <1>; 34*4882a593Smuzhiyun #size-cells = <0>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 37*4882a593Smuzhiyun reg = <0>; 38*4882a593Smuzhiyun remote-endpoint = <&mipi_csi2_input>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&i2c1 { 45*4882a593Smuzhiyun status = "okay"; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /delete-node/ sc210iot@32; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun imx415: imx415@1a { 50*4882a593Smuzhiyun compatible = "sony,imx415"; 51*4882a593Smuzhiyun reg = <0x1a>; 52*4882a593Smuzhiyun clocks = <&cru CLK_MIPICSI_OUT>; 53*4882a593Smuzhiyun clock-names = "xvclk"; 54*4882a593Smuzhiyun power-domains = <&power RV1126_PD_VI>; 55*4882a593Smuzhiyun avdd-supply = <&vcc2v8_avdd>; 56*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dovdd>; 57*4882a593Smuzhiyun dvdd-supply = <&vcc1v2_dvdd>; 58*4882a593Smuzhiyun pwd-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; 59*4882a593Smuzhiyun reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 60*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 61*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 62*4882a593Smuzhiyun rockchip,camera-module-name = "YT10092"; 63*4882a593Smuzhiyun rockchip,camera-module-lens-name = "IR0147-36IRC-8M-F20"; 64*4882a593Smuzhiyun ir-cut = <&cam_ircut0>; 65*4882a593Smuzhiyun port { 66*4882a593Smuzhiyun ucam_out0: endpoint { 67*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 68*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&isp_reserved { 75*4882a593Smuzhiyun size = <0x0AC00000>; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&mipi_csi2 { 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun ports { 82*4882a593Smuzhiyun #address-cells = <1>; 83*4882a593Smuzhiyun #size-cells = <0>; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun port@0 { 86*4882a593Smuzhiyun reg = <0>; 87*4882a593Smuzhiyun #address-cells = <1>; 88*4882a593Smuzhiyun #size-cells = <0>; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun mipi_csi2_input: endpoint@1 { 91*4882a593Smuzhiyun reg = <1>; 92*4882a593Smuzhiyun remote-endpoint = <&csidphy0_out>; 93*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun port@1 { 98*4882a593Smuzhiyun reg = <1>; 99*4882a593Smuzhiyun #address-cells = <1>; 100*4882a593Smuzhiyun #size-cells = <0>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun mipi_csi2_output: endpoint@0 { 103*4882a593Smuzhiyun reg = <0>; 104*4882a593Smuzhiyun remote-endpoint = <&cif_mipi_in>; 105*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&rkcif { 112*4882a593Smuzhiyun status = "okay"; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun&rkcif_mipi_lvds { 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun port { 119*4882a593Smuzhiyun /* MIPI CSI-2 endpoint */ 120*4882a593Smuzhiyun cif_mipi_in: endpoint { 121*4882a593Smuzhiyun remote-endpoint = <&mipi_csi2_output>; 122*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun}; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf { 128*4882a593Smuzhiyun status = "okay"; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun port { 131*4882a593Smuzhiyun /* MIPI CSI-2 endpoint */ 132*4882a593Smuzhiyun mipi_lvds_sditf: endpoint { 133*4882a593Smuzhiyun remote-endpoint = <&isp_in>; 134*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun}; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun&rkisp_thunderboot { 140*4882a593Smuzhiyun reg = <0x8000000 (128 * 0x00100000)>; 141*4882a593Smuzhiyun}; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun&isp_in { 144*4882a593Smuzhiyun remote-endpoint = <&mipi_lvds_sditf>; 145*4882a593Smuzhiyun}; 146