xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/rv1126-38x38-v10-emmc.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include "rv1126.dtsi"
8*4882a593Smuzhiyun#include "rv1126-ipc.dtsi"
9*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "Rockchip RV1126 38x38 V10 EMMC DDR3 Board";
13*4882a593Smuzhiyun	compatible = "rockchip,rv1126-38x38-v10-emmc", "rockchip,rv1126";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	chosen {
16*4882a593Smuzhiyun		bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait snd_aloop.index=7";
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	/delete-node/ vdd-npu;
20*4882a593Smuzhiyun	/delete-node/ vdd-vepu;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	vcc_1v8: vcc-1v8 {
23*4882a593Smuzhiyun		compatible = "regulator-fixed";
24*4882a593Smuzhiyun		regulator-name = "vcc_1v8";
25*4882a593Smuzhiyun		regulator-always-on;
26*4882a593Smuzhiyun		regulator-boot-on;
27*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
28*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	vcc_dvdd: vcc-dvdd {
32*4882a593Smuzhiyun		compatible = "regulator-fixed";
33*4882a593Smuzhiyun		regulator-name = "vcc_dvdd";
34*4882a593Smuzhiyun		regulator-always-on;
35*4882a593Smuzhiyun		regulator-boot-on;
36*4882a593Smuzhiyun		regulator-min-microvolt = <1200000>;
37*4882a593Smuzhiyun		regulator-max-microvolt = <1200000>;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	vcc3v3_sys: vcc33sys {
41*4882a593Smuzhiyun		compatible = "regulator-fixed";
42*4882a593Smuzhiyun		regulator-name = "vcc3v3_sys";
43*4882a593Smuzhiyun		regulator-always-on;
44*4882a593Smuzhiyun		regulator-boot-on;
45*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
46*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
47*4882a593Smuzhiyun	};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun	vcc_sd: vcc-sd {
50*4882a593Smuzhiyun		compatible = "regulator-fixed";
51*4882a593Smuzhiyun		gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
52*4882a593Smuzhiyun		pinctrl-0 = <&sdmmc_pwr>;
53*4882a593Smuzhiyun		pinctrl-names = "default";
54*4882a593Smuzhiyun		regulator-name = "vcc_sd";
55*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
56*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
57*4882a593Smuzhiyun		startup-delay-us = <100000>;
58*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
59*4882a593Smuzhiyun		enable-active-high;
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	vdd_arm: vdd-arm {
63*4882a593Smuzhiyun		compatible = "pwm-regulator";
64*4882a593Smuzhiyun		pwms = <&pwm0 0 5000 1>;
65*4882a593Smuzhiyun		regulator-name = "vdd_arm";
66*4882a593Smuzhiyun		regulator-min-microvolt = <720000>;
67*4882a593Smuzhiyun		regulator-max-microvolt = <1000000>;
68*4882a593Smuzhiyun		regulator-init-microvolt = <825000>;
69*4882a593Smuzhiyun		regulator-always-on;
70*4882a593Smuzhiyun		regulator-boot-on;
71*4882a593Smuzhiyun		regulator-settling-time-up-us = <250>;
72*4882a593Smuzhiyun		pwm-supply = <&vcc3v3_sys>;
73*4882a593Smuzhiyun		status = "okay";
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	/*
77*4882a593Smuzhiyun	 * pwm1 is reserved as voltage adjustment in hardware
78*4882a593Smuzhiyun	 * use fixed regulator to avoid voltage adjustment by software
79*4882a593Smuzhiyun	 */
80*4882a593Smuzhiyun	vdd_logic_npu_vepu: vdd-logic-npu-vepu {
81*4882a593Smuzhiyun		compatible = "pwm-regulator";
82*4882a593Smuzhiyun		pwms = <&pwm1 0 5000 1>;
83*4882a593Smuzhiyun		regulator-name = "vdd_logic_npu_vepu";
84*4882a593Smuzhiyun		regulator-min-microvolt = <720000>;
85*4882a593Smuzhiyun		regulator-max-microvolt = <880000>;
86*4882a593Smuzhiyun		regulator-init-microvolt = <825000>;
87*4882a593Smuzhiyun		regulator-always-on;
88*4882a593Smuzhiyun		regulator-boot-on;
89*4882a593Smuzhiyun		regulator-settling-time-up-us = <250>;
90*4882a593Smuzhiyun		pwm-supply = <&vcc3v3_sys>;
91*4882a593Smuzhiyun		status = "okay";
92*4882a593Smuzhiyun	};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun	vdd_logic_npu_vepu_fixed: vdd-logic-npu-vepu-fixed {
95*4882a593Smuzhiyun		compatible = "regulator-fixed";
96*4882a593Smuzhiyun		regulator-name = "vdd_logic_npu_vepu-fixed";
97*4882a593Smuzhiyun		regulator-always-on;
98*4882a593Smuzhiyun		regulator-boot-on;
99*4882a593Smuzhiyun		regulator-min-microvolt = <825000>;
100*4882a593Smuzhiyun		regulator-max-microvolt = <825000>;
101*4882a593Smuzhiyun	};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	adc-keys {
104*4882a593Smuzhiyun		compatible = "adc-keys";
105*4882a593Smuzhiyun		io-channels = <&saradc 0>;
106*4882a593Smuzhiyun		io-channel-names = "buttons";
107*4882a593Smuzhiyun		poll-interval = <100>;
108*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun		esc-key {
111*4882a593Smuzhiyun			label = "esc";
112*4882a593Smuzhiyun			linux,code = <KEY_ESC>;
113*4882a593Smuzhiyun			press-threshold-microvolt = <0>;
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	cam_ircut0: cam_ircut {
118*4882a593Smuzhiyun		status = "okay";
119*4882a593Smuzhiyun		compatible = "rockchip,ircut";
120*4882a593Smuzhiyun		ircut-open-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
121*4882a593Smuzhiyun		ircut-close-gpios  = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
122*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
123*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun	flash_ir: flash-ir {
127*4882a593Smuzhiyun		status = "okay";
128*4882a593Smuzhiyun		compatible = "led,rgb13h";
129*4882a593Smuzhiyun		label = "pwm-flash-ir";
130*4882a593Smuzhiyun		led-max-microamp = <20000>;
131*4882a593Smuzhiyun		flash-max-microamp = <20000>;
132*4882a593Smuzhiyun		flash-max-timeout-us = <1000000>;
133*4882a593Smuzhiyun		pwms=<&pwm3 0 25000 0>;
134*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
135*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
136*4882a593Smuzhiyun	};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun	i2s0_sound: i2s0-sound {
139*4882a593Smuzhiyun		status = "okay";
140*4882a593Smuzhiyun		compatible = "simple-audio-card";
141*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
142*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
143*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,i2s0-sound";
144*4882a593Smuzhiyun		simple-audio-card,cpu {
145*4882a593Smuzhiyun			sound-dai = <&i2s0_8ch>;
146*4882a593Smuzhiyun		};
147*4882a593Smuzhiyun		simple-audio-card,codec {
148*4882a593Smuzhiyun			sound-dai = <&es8311>;
149*4882a593Smuzhiyun		};
150*4882a593Smuzhiyun	};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
153*4882a593Smuzhiyun		compatible = "wlan-platdata";
154*4882a593Smuzhiyun		rockchip,grf = <&grf>;
155*4882a593Smuzhiyun		wifi_chip_type = "USB-WiFi";
156*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
157*4882a593Smuzhiyun		status = "okay";
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun&csi_dphy0 {
162*4882a593Smuzhiyun	status = "okay";
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun	ports {
165*4882a593Smuzhiyun		#address-cells = <1>;
166*4882a593Smuzhiyun		#size-cells = <0>;
167*4882a593Smuzhiyun		port@0 {
168*4882a593Smuzhiyun			reg = <0>;
169*4882a593Smuzhiyun			#address-cells = <1>;
170*4882a593Smuzhiyun			#size-cells = <0>;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
173*4882a593Smuzhiyun				reg = <1>;
174*4882a593Smuzhiyun				remote-endpoint = <&ucam_out0>;
175*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
176*4882a593Smuzhiyun			};
177*4882a593Smuzhiyun		};
178*4882a593Smuzhiyun		port@1 {
179*4882a593Smuzhiyun			reg = <1>;
180*4882a593Smuzhiyun			#address-cells = <1>;
181*4882a593Smuzhiyun			#size-cells = <0>;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun			csidphy0_out: endpoint@0 {
184*4882a593Smuzhiyun				reg = <0>;
185*4882a593Smuzhiyun				remote-endpoint = <&mipi_csi2_input>;
186*4882a593Smuzhiyun			};
187*4882a593Smuzhiyun		};
188*4882a593Smuzhiyun	};
189*4882a593Smuzhiyun};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun&emmc {
192*4882a593Smuzhiyun	bus-width = <8>;
193*4882a593Smuzhiyun	cap-mmc-highspeed;
194*4882a593Smuzhiyun	non-removable;
195*4882a593Smuzhiyun	mmc-hs200-1_8v;
196*4882a593Smuzhiyun	rockchip,default-sample-phase = <90>;
197*4882a593Smuzhiyun	no-sdio;
198*4882a593Smuzhiyun	no-sd;
199*4882a593Smuzhiyun	/delete-property/ pinctrl-names;
200*4882a593Smuzhiyun	/delete-property/ pinctrl-0;
201*4882a593Smuzhiyun	status = "okay";
202*4882a593Smuzhiyun};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun&gmac {
205*4882a593Smuzhiyun	phy-mode = "rmii";
206*4882a593Smuzhiyun	clock_in_out = "output";
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
209*4882a593Smuzhiyun	snps,reset-active-low;
210*4882a593Smuzhiyun	snps,reset-delays-us = <0 50000 10000>;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun	assigned-clocks = <&cru CLK_GMAC_SRC_M0>, <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>;
213*4882a593Smuzhiyun	assigned-clock-rates = <0>, <50000000>;
214*4882a593Smuzhiyun	assigned-clock-parents = <&cru CLK_GMAC_RGMII_M0>, <&cru CLK_GMAC_SRC_M0>, <&cru RMII_MODE_CLK>;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun	pinctrl-names = "default";
217*4882a593Smuzhiyun	pinctrl-0 = <&rmiim0_miim &rgmiim0_rxer &rmiim0_bus2 &rgmiim0_mclkinout>;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun	phy-handle = <&phy>;
220*4882a593Smuzhiyun	status = "okay";
221*4882a593Smuzhiyun};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun&i2c0 {
224*4882a593Smuzhiyun	status = "okay";
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun	pcf8563: pcf8563@51 {
227*4882a593Smuzhiyun		compatible = "pcf8563";
228*4882a593Smuzhiyun		reg = <0x51>;
229*4882a593Smuzhiyun		#clock-cells = <0>;
230*4882a593Smuzhiyun		clock-frequency = <32768>;
231*4882a593Smuzhiyun		clock-output-names = "xin32k";
232*4882a593Smuzhiyun	};
233*4882a593Smuzhiyun};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun&i2c1 {
236*4882a593Smuzhiyun	status = "okay";
237*4882a593Smuzhiyun	clock-frequency = <400000>;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun	imx415: imx415@1a {
240*4882a593Smuzhiyun		   compatible = "sony,imx415";
241*4882a593Smuzhiyun		   reg = <0x1a>;
242*4882a593Smuzhiyun		   clocks = <&cru CLK_MIPICSI_OUT>;
243*4882a593Smuzhiyun		   clock-names = "xvclk";
244*4882a593Smuzhiyun		   power-domains = <&power RV1126_PD_VI>;
245*4882a593Smuzhiyun		   pinctrl-names = "rockchip,camera_default";
246*4882a593Smuzhiyun		   pinctrl-0 = <&mipicsi_clk0>;
247*4882a593Smuzhiyun		   avdd-supply = <&vcc3v3_sys>;
248*4882a593Smuzhiyun		   dovdd-supply = <&vcc_1v8>;
249*4882a593Smuzhiyun		   dvdd-supply = <&vcc_dvdd>;
250*4882a593Smuzhiyun		   /* reset is always pulled high in v10 */
251*4882a593Smuzhiyun		   reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
252*4882a593Smuzhiyun		   rockchip,camera-module-index = <1>;
253*4882a593Smuzhiyun		   rockchip,camera-module-facing = "front";
254*4882a593Smuzhiyun		   rockchip,camera-module-name = "YT10092";
255*4882a593Smuzhiyun		   rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
256*4882a593Smuzhiyun		   ir-cut = <&cam_ircut0>;
257*4882a593Smuzhiyun		   flash-leds = <&flash_ir>;
258*4882a593Smuzhiyun		   port {
259*4882a593Smuzhiyun				   ucam_out0: endpoint {
260*4882a593Smuzhiyun						   remote-endpoint = <&mipi_in_ucam0>;
261*4882a593Smuzhiyun						   data-lanes = <1 2 3 4>;
262*4882a593Smuzhiyun				   };
263*4882a593Smuzhiyun		   };
264*4882a593Smuzhiyun	};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun&i2c4 {
269*4882a593Smuzhiyun	status = "okay";
270*4882a593Smuzhiyun	clock-frequency = <400000>;
271*4882a593Smuzhiyun	pinctrl-0 = <&i2c4m1_xfer>;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun	es8311: es8311@18 {
274*4882a593Smuzhiyun		compatible = "everest,es8311";
275*4882a593Smuzhiyun		reg = <0x18>;
276*4882a593Smuzhiyun		clocks = <&cru MCLK_I2S0_TX_OUT2IO>;
277*4882a593Smuzhiyun		clock-names = "mclk";
278*4882a593Smuzhiyun		adc-volume = <0xbf>;  /* 0dB */
279*4882a593Smuzhiyun		dac-volume = <0xbf>;  /* 0dB */
280*4882a593Smuzhiyun		aec-mode = "dac left, adc right";
281*4882a593Smuzhiyun		pinctrl-names = "default";
282*4882a593Smuzhiyun		pinctrl-0 = <&i2s0m0_mclk &spk_ctl>;
283*4882a593Smuzhiyun		assigned-clocks = <&cru MCLK_I2S0_TX_OUT2IO>;
284*4882a593Smuzhiyun		assigned-clock-parents = <&cru MCLK_I2S0_TX>;
285*4882a593Smuzhiyun		spk-ctl-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
286*4882a593Smuzhiyun		#sound-dai-cells = <0>;
287*4882a593Smuzhiyun	};
288*4882a593Smuzhiyun};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun&i2s0_8ch {
291*4882a593Smuzhiyun	status = "okay";
292*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
293*4882a593Smuzhiyun	#sound-dai-cells = <0>;
294*4882a593Smuzhiyun	pinctrl-0 = <&i2s0m0_sclk_tx
295*4882a593Smuzhiyun		     &i2s0m0_lrck_tx
296*4882a593Smuzhiyun		     &i2s0m0_sdi0
297*4882a593Smuzhiyun		     &i2s0m0_sdo0>;
298*4882a593Smuzhiyun};
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun&isp_reserved {
301*4882a593Smuzhiyun	size = <0x20000000>;
302*4882a593Smuzhiyun};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun&mdio {
305*4882a593Smuzhiyun	phy: phy@1 {
306*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
307*4882a593Smuzhiyun		reg = <0x1>;
308*4882a593Smuzhiyun	};
309*4882a593Smuzhiyun};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun&mipi_csi2 {
312*4882a593Smuzhiyun	status = "okay";
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun	ports {
315*4882a593Smuzhiyun		#address-cells = <1>;
316*4882a593Smuzhiyun		#size-cells = <0>;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun		port@0 {
319*4882a593Smuzhiyun			reg = <0>;
320*4882a593Smuzhiyun			#address-cells = <1>;
321*4882a593Smuzhiyun			#size-cells = <0>;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun			mipi_csi2_input: endpoint@1 {
324*4882a593Smuzhiyun				reg = <1>;
325*4882a593Smuzhiyun				remote-endpoint = <&csidphy0_out>;
326*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
327*4882a593Smuzhiyun			};
328*4882a593Smuzhiyun		};
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun		port@1 {
331*4882a593Smuzhiyun			reg = <1>;
332*4882a593Smuzhiyun			#address-cells = <1>;
333*4882a593Smuzhiyun			#size-cells = <0>;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun			mipi_csi2_output: endpoint@0 {
336*4882a593Smuzhiyun				reg = <0>;
337*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in>;
338*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
339*4882a593Smuzhiyun			};
340*4882a593Smuzhiyun		};
341*4882a593Smuzhiyun	};
342*4882a593Smuzhiyun};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun&npu {
345*4882a593Smuzhiyun	npu-supply = <&vdd_logic_npu_vepu_fixed>;
346*4882a593Smuzhiyun};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun&npu_opp_table {
349*4882a593Smuzhiyun	/delete-node/ opp-800000000;
350*4882a593Smuzhiyun	/delete-node/ opp-934000000;
351*4882a593Smuzhiyun};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun&pinctrl {
354*4882a593Smuzhiyun	es8311 {
355*4882a593Smuzhiyun		spk_ctl: spk-ctl {
356*4882a593Smuzhiyun			rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
357*4882a593Smuzhiyun		};
358*4882a593Smuzhiyun	};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun	sdmmc-pwr {
361*4882a593Smuzhiyun		/omit-if-no-ref/
362*4882a593Smuzhiyun		sdmmc_pwr: sdmmc-pwr {
363*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
364*4882a593Smuzhiyun		};
365*4882a593Smuzhiyun	};
366*4882a593Smuzhiyun};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun&pmu_io_domains {
369*4882a593Smuzhiyun	status = "okay";
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun	pmuio0-supply = <&vcc3v3_sys>;
372*4882a593Smuzhiyun	pmuio1-supply = <&vcc3v3_sys>;
373*4882a593Smuzhiyun	vccio2-supply = <&vcc3v3_sys>;
374*4882a593Smuzhiyun	vccio3-supply = <&vcc3v3_sys>;
375*4882a593Smuzhiyun	vccio4-supply = <&vcc_1v8>;
376*4882a593Smuzhiyun	vccio5-supply = <&vcc3v3_sys>;
377*4882a593Smuzhiyun	vccio6-supply = <&vcc3v3_sys>;
378*4882a593Smuzhiyun	vccio7-supply = <&vcc3v3_sys>;
379*4882a593Smuzhiyun};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun&pwm3 {
382*4882a593Smuzhiyun	status = "okay";
383*4882a593Smuzhiyun	pinctrl-names = "active";
384*4882a593Smuzhiyun	pinctrl-0 = <&pwm3m0_pins_pull_down>;
385*4882a593Smuzhiyun};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun&rkcif {
388*4882a593Smuzhiyun	status = "okay";
389*4882a593Smuzhiyun};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun&rkcif_mmu {
392*4882a593Smuzhiyun	status = "disabled";
393*4882a593Smuzhiyun};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun&rkcif_mipi_lvds {
396*4882a593Smuzhiyun	status = "okay";
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun	port {
399*4882a593Smuzhiyun		/* MIPI CSI-2 endpoint */
400*4882a593Smuzhiyun		cif_mipi_in: endpoint {
401*4882a593Smuzhiyun			remote-endpoint = <&mipi_csi2_output>;
402*4882a593Smuzhiyun			data-lanes = <1 2 3 4>;
403*4882a593Smuzhiyun		};
404*4882a593Smuzhiyun	};
405*4882a593Smuzhiyun};
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf {
408*4882a593Smuzhiyun	status = "okay";
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun	port {
411*4882a593Smuzhiyun		/* MIPI CSI-2 endpoint */
412*4882a593Smuzhiyun		mipi_lvds_sditf: endpoint {
413*4882a593Smuzhiyun			remote-endpoint = <&isp_in>;
414*4882a593Smuzhiyun			data-lanes = <1 2 3 4>;
415*4882a593Smuzhiyun		};
416*4882a593Smuzhiyun	};
417*4882a593Smuzhiyun};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun&rkisp_vir0 {
420*4882a593Smuzhiyun	status = "okay";
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun	ports {
423*4882a593Smuzhiyun		port@0 {
424*4882a593Smuzhiyun			reg = <0>;
425*4882a593Smuzhiyun			#address-cells = <1>;
426*4882a593Smuzhiyun			#size-cells = <0>;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun			isp_in: endpoint@0 {
429*4882a593Smuzhiyun				reg = <0>;
430*4882a593Smuzhiyun				remote-endpoint = <&mipi_lvds_sditf>;
431*4882a593Smuzhiyun			};
432*4882a593Smuzhiyun		};
433*4882a593Smuzhiyun	};
434*4882a593Smuzhiyun};
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun&rkvenc {
437*4882a593Smuzhiyun	venc-supply = <&vdd_logic_npu_vepu_fixed>;
438*4882a593Smuzhiyun};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun&rockchip_suspend {
441*4882a593Smuzhiyun	status = "okay";
442*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
443*4882a593Smuzhiyun	rockchip,sleep-mode-config = <
444*4882a593Smuzhiyun		(0
445*4882a593Smuzhiyun		| RKPM_SLP_ARMOFF
446*4882a593Smuzhiyun		| RKPM_SLP_PMU_PMUALIVE_32K
447*4882a593Smuzhiyun		| RKPM_SLP_PMU_DIS_OSC
448*4882a593Smuzhiyun		)
449*4882a593Smuzhiyun	>;
450*4882a593Smuzhiyun};
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun&saradc {
453*4882a593Smuzhiyun	status = "okay";
454*4882a593Smuzhiyun	vref-supply = <&vcc_1v8>;
455*4882a593Smuzhiyun};
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun&sdmmc0_bus4 {
458*4882a593Smuzhiyun	rockchip,pins =
459*4882a593Smuzhiyun		/* sdmmc0_d0 */
460*4882a593Smuzhiyun		<1 RK_PA4 1 &pcfg_pull_up_drv_level_0>,
461*4882a593Smuzhiyun		/* sdmmc0_d1 */
462*4882a593Smuzhiyun		<1 RK_PA5 1 &pcfg_pull_up_drv_level_0>,
463*4882a593Smuzhiyun		/* sdmmc0_d2 */
464*4882a593Smuzhiyun		<1 RK_PA6 1 &pcfg_pull_up_drv_level_0>,
465*4882a593Smuzhiyun		/* sdmmc0_d3 */
466*4882a593Smuzhiyun		<1 RK_PA7 1 &pcfg_pull_up_drv_level_0>;
467*4882a593Smuzhiyun};
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun&sdmmc0_clk {
470*4882a593Smuzhiyun	rockchip,pins =
471*4882a593Smuzhiyun		/* sdmmc0_clk */
472*4882a593Smuzhiyun		<1 RK_PB0 1 &pcfg_pull_up_drv_level_3>;
473*4882a593Smuzhiyun};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun&sdmmc0_cmd {
476*4882a593Smuzhiyun	rockchip,pins =
477*4882a593Smuzhiyun		/* sdmmc0_cmd */
478*4882a593Smuzhiyun		<1 RK_PB1 1 &pcfg_pull_up_drv_level_0>;
479*4882a593Smuzhiyun};
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun&sdmmc {
482*4882a593Smuzhiyun	bus-width = <4>;
483*4882a593Smuzhiyun	cap-mmc-highspeed;
484*4882a593Smuzhiyun	cap-sd-highspeed;
485*4882a593Smuzhiyun	card-detect-delay = <200>;
486*4882a593Smuzhiyun	rockchip,default-sample-phase = <90>;
487*4882a593Smuzhiyun	no-sdio;
488*4882a593Smuzhiyun	no-mmc;
489*4882a593Smuzhiyun	status = "okay";
490*4882a593Smuzhiyun	vmmc-supply = <&vcc_sd>;
491*4882a593Smuzhiyun};
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun&soc_crit {
494*4882a593Smuzhiyun	/* millicelsius */
495*4882a593Smuzhiyun	temperature = <125000>;
496*4882a593Smuzhiyun};
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun&u2phy1 {
499*4882a593Smuzhiyun	status = "okay";
500*4882a593Smuzhiyun	u2phy_host: host-port {
501*4882a593Smuzhiyun		status = "okay";
502*4882a593Smuzhiyun	};
503*4882a593Smuzhiyun};
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun&uart3 {
506*4882a593Smuzhiyun	wakeup-source;
507*4882a593Smuzhiyun	pinctrl-names = "default";
508*4882a593Smuzhiyun	pinctrl-0 = <&uart3m2_xfer &uart3m2_ctsn &uart3m2_rtsn>;
509*4882a593Smuzhiyun	status = "okay";
510*4882a593Smuzhiyun};
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun&usb_host0_ehci {
513*4882a593Smuzhiyun	status = "okay";
514*4882a593Smuzhiyun};
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun&usb_host0_ohci {
517*4882a593Smuzhiyun	status = "okay";
518*4882a593Smuzhiyun};
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun&wdt {
521*4882a593Smuzhiyun	status = "okay";
522*4882a593Smuzhiyun};
523