1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun#include "rv1109.dtsi" 7*4882a593Smuzhiyun#include "rv1126-evb-v12.dtsi" 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun model = "Rockchip RV1109 V12 FACIAL GATE Board"; 10*4882a593Smuzhiyun compatible = "rockchip,rv1109-evb-ddr3-v12-facial-gate", "rockchip,rv1109"; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun chosen { 13*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait snd_aloop.index=7"; 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun pwmleds { 17*4882a593Smuzhiyun compatible = "pwm-leds"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun pwmi_ir { 20*4882a593Smuzhiyun label = "PWM-IR"; 21*4882a593Smuzhiyun pwms = <&pwm11 0 25000 0>; 22*4882a593Smuzhiyun max-brightness = <255>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun vcc1v2_dvdd: vcc1v2-dvdd { 27*4882a593Smuzhiyun compatible = "regulator-fixed"; 28*4882a593Smuzhiyun regulator-name = "vcc1v2_dvdd"; 29*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 30*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun vcc2v8_avdd: vcc2v8-avdd { 34*4882a593Smuzhiyun compatible = "regulator-fixed"; 35*4882a593Smuzhiyun regulator-name = "vcc2v8_avdd"; 36*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 37*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&csi_dphy0 { 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun ports { 44*4882a593Smuzhiyun port@0 { 45*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 46*4882a593Smuzhiyun remote-endpoint = <&ucam_out0>; 47*4882a593Smuzhiyun data-lanes = <1 2>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun port@1 { 51*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 52*4882a593Smuzhiyun remote-endpoint = <&mipi_csi2_input>; 53*4882a593Smuzhiyun data-lanes = <1 2>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun&csi_dphy1 { 60*4882a593Smuzhiyun status = "okay"; 61*4882a593Smuzhiyun ports { 62*4882a593Smuzhiyun port@0 { 63*4882a593Smuzhiyun csi_dphy1_input: endpoint@1 { 64*4882a593Smuzhiyun remote-endpoint = <&ucam_out1>; 65*4882a593Smuzhiyun data-lanes = <1 2>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun port@1 { 69*4882a593Smuzhiyun csi_dphy1_output: endpoint@0 { 70*4882a593Smuzhiyun remote-endpoint = <&isp_in>; 71*4882a593Smuzhiyun data-lanes = <1 2>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun}; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun&i2c1 { 78*4882a593Smuzhiyun /delete-node/ ar0230@10; 79*4882a593Smuzhiyun /delete-node/ ov4689@36; 80*4882a593Smuzhiyun /delete-node/ os04a10@36; 81*4882a593Smuzhiyun ov2718: ov2718@10 { 82*4882a593Smuzhiyun compatible = "ovti,ov2718"; 83*4882a593Smuzhiyun reg = <0x10>; 84*4882a593Smuzhiyun clocks = <&cru CLK_MIPICSI_OUT>; 85*4882a593Smuzhiyun clock-names = "xvclk"; 86*4882a593Smuzhiyun power-domains = <&power RV1126_PD_VI>; 87*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 88*4882a593Smuzhiyun pinctrl-0 = <&mipicsi_clk1>; 89*4882a593Smuzhiyun avdd-supply = <&vcc_avdd>; 90*4882a593Smuzhiyun dovdd-supply = <&vcc_dovdd>; 91*4882a593Smuzhiyun dvdd-supply = <&vcc_dvdd>; 92*4882a593Smuzhiyun pwd-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; 93*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; 94*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 95*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 96*4882a593Smuzhiyun rockchip,camera-module-name = "YT-RV1109-3-V1"; 97*4882a593Smuzhiyun rockchip,camera-module-lens-name = "M43-4IR-2MP-F2"; 98*4882a593Smuzhiyun ir-cut = <&cam_ircut0>; 99*4882a593Smuzhiyun port { 100*4882a593Smuzhiyun ucam_out1: endpoint { 101*4882a593Smuzhiyun remote-endpoint = <&csi_dphy1_input>; 102*4882a593Smuzhiyun data-lanes = <1 2>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun gc2053: gc2053@37 { 108*4882a593Smuzhiyun compatible = "galaxycore,gc2053"; 109*4882a593Smuzhiyun reg = <0x37>; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun clocks = <&cru CLK_MIPICSI_OUT>; 112*4882a593Smuzhiyun clock-names = "xvclk"; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun power-domains = <&power RV1126_PD_VI>; 115*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 116*4882a593Smuzhiyun pinctrl-0 = <&mipicsi_clk0>; 117*4882a593Smuzhiyun power-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 118*4882a593Smuzhiyun pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_LOW>; 119*4882a593Smuzhiyun reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun avdd-supply = <&vcc2v8_avdd>; 122*4882a593Smuzhiyun dovdd-supply = <&vcc_dovdd>; 123*4882a593Smuzhiyun dvdd-supply = <&vcc1v2_dvdd>; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 126*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 127*4882a593Smuzhiyun rockchip,camera-module-name = "YT-RV1109-2-V1"; 128*4882a593Smuzhiyun rockchip,camera-module-lens-name = "40IR-2MP-F20"; 129*4882a593Smuzhiyun port { 130*4882a593Smuzhiyun ucam_out0: endpoint { 131*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 132*4882a593Smuzhiyun data-lanes = <1 2>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun/* isp cma buffer don't fiddle with it, dual camera(1920 * 1080) need 92M buffer */ 139*4882a593Smuzhiyun&isp_reserved { 140*4882a593Smuzhiyun size = <0x5c00000>; 141*4882a593Smuzhiyun}; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun&mipi_csi2 { 144*4882a593Smuzhiyun status = "okay"; 145*4882a593Smuzhiyun ports { 146*4882a593Smuzhiyun port@0 { 147*4882a593Smuzhiyun mipi_csi2_input: endpoint@1 { 148*4882a593Smuzhiyun remote-endpoint = <&csidphy0_out>; 149*4882a593Smuzhiyun data-lanes = <1 2>; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun port@1 { 154*4882a593Smuzhiyun mipi_csi2_output: endpoint@0 { 155*4882a593Smuzhiyun remote-endpoint = <&cif_mipi_in>; 156*4882a593Smuzhiyun data-lanes = <1 2>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun}; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun&pwm11 { 163*4882a593Smuzhiyun status = "okay"; 164*4882a593Smuzhiyun pinctrl-names = "active"; 165*4882a593Smuzhiyun pinctrl-0 = <&pwm11m1_pins_pull_down>; 166*4882a593Smuzhiyun}; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun&rk809 { 169*4882a593Smuzhiyun regulators { 170*4882a593Smuzhiyun vcc_dvdd: LDO_REG6 { 171*4882a593Smuzhiyun regulator-min-microvolt = <1300000>; 172*4882a593Smuzhiyun regulator-max-microvolt = <1300000>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun vcc_avdd: LDO_REG7 { 176*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 177*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun}; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun&rkcif_mipi_lvds { 183*4882a593Smuzhiyun status = "okay"; 184*4882a593Smuzhiyun port { 185*4882a593Smuzhiyun cif_mipi_in: endpoint { 186*4882a593Smuzhiyun remote-endpoint = <&mipi_csi2_output>; 187*4882a593Smuzhiyun data-lanes = <1 2>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun}; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf { 193*4882a593Smuzhiyun status = "okay"; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun port { 196*4882a593Smuzhiyun cif_sditf: endpoint { 197*4882a593Smuzhiyun remote-endpoint = <&isp_virt1_in>; 198*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&rkisp_vir0 { 204*4882a593Smuzhiyun ports { 205*4882a593Smuzhiyun port@0 { 206*4882a593Smuzhiyun isp_in: endpoint@0 { 207*4882a593Smuzhiyun remote-endpoint = <&csi_dphy1_output>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun}; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun&rkisp_vir1 { 214*4882a593Smuzhiyun status = "okay"; 215*4882a593Smuzhiyun ports { 216*4882a593Smuzhiyun port@0 { 217*4882a593Smuzhiyun reg = <0>; 218*4882a593Smuzhiyun #address-cells = <1>; 219*4882a593Smuzhiyun #size-cells = <0>; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun isp_virt1_in: endpoint@0 { 222*4882a593Smuzhiyun reg = <0>; 223*4882a593Smuzhiyun remote-endpoint = <&cif_sditf>; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun}; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun&rkispp_vir1 { 230*4882a593Smuzhiyun status = "okay"; 231*4882a593Smuzhiyun}; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun&rkispp { 234*4882a593Smuzhiyun status = "okay"; 235*4882a593Smuzhiyun /* the max input w h and fps of mulit sensor */ 236*4882a593Smuzhiyun max-input = <1920 1080 30>; 237*4882a593Smuzhiyun}; 238