xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/rv1109-38-v10-spi-nand.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include "rv1109.dtsi"
8*4882a593Smuzhiyun#include "rv1126-ipc.dtsi"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	model = "Rockchip RV1109 38 V10 SPI NAND DDR3 Board";
12*4882a593Smuzhiyun	compatible = "rockchip,rv1109-38-v10-spi-nand", "rockchip,rv1109";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	chosen {
15*4882a593Smuzhiyun		bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs snd_aloop.index=7";
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	/delete-node/ vdd-npu;
19*4882a593Smuzhiyun	/delete-node/ vdd-vepu;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	cam_ircut0: cam_ircut {
22*4882a593Smuzhiyun		compatible = "rockchip,ircut";
23*4882a593Smuzhiyun		status = "okay";
24*4882a593Smuzhiyun		ircut-open-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
25*4882a593Smuzhiyun		ircut-close-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
26*4882a593Smuzhiyun		pinctrl-names = "default";
27*4882a593Smuzhiyun		pinctrl-0 = <&ircut_pins>;
28*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
29*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	vcc_1v8: vcc-1v8 {
33*4882a593Smuzhiyun		compatible = "regulator-fixed";
34*4882a593Smuzhiyun		regulator-name = "vcc_1v8";
35*4882a593Smuzhiyun		regulator-always-on;
36*4882a593Smuzhiyun		regulator-boot-on;
37*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
38*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	vcc_dvdd: vcc-dvdd {
42*4882a593Smuzhiyun		compatible = "regulator-fixed";
43*4882a593Smuzhiyun		regulator-name = "vcc_dvdd";
44*4882a593Smuzhiyun		regulator-always-on;
45*4882a593Smuzhiyun		regulator-boot-on;
46*4882a593Smuzhiyun		regulator-min-microvolt = <1200000>;
47*4882a593Smuzhiyun		regulator-max-microvolt = <1200000>;
48*4882a593Smuzhiyun	};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun	vcc3v3_sys: vcc33sys {
51*4882a593Smuzhiyun		compatible = "regulator-fixed";
52*4882a593Smuzhiyun		regulator-name = "vcc3v3_sys";
53*4882a593Smuzhiyun		regulator-always-on;
54*4882a593Smuzhiyun		regulator-boot-on;
55*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
56*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
57*4882a593Smuzhiyun	};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun	vcc_sd: vcc-sd {
60*4882a593Smuzhiyun		compatible = "regulator-fixed";
61*4882a593Smuzhiyun		gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
62*4882a593Smuzhiyun		pinctrl-0 = <&sdmmc_pwr>;
63*4882a593Smuzhiyun		pinctrl-names = "default";
64*4882a593Smuzhiyun		regulator-name = "vcc_sd";
65*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
66*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
67*4882a593Smuzhiyun		startup-delay-us = <100000>;
68*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
69*4882a593Smuzhiyun		enable-active-high;
70*4882a593Smuzhiyun	};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun	vdd_arm: vdd-arm {
73*4882a593Smuzhiyun		compatible = "pwm-regulator";
74*4882a593Smuzhiyun		pwms = <&pwm0 0 5000 1>;
75*4882a593Smuzhiyun		regulator-name = "vdd_arm";
76*4882a593Smuzhiyun		regulator-min-microvolt = <720000>;
77*4882a593Smuzhiyun		regulator-max-microvolt = <1000000>;
78*4882a593Smuzhiyun		regulator-init-microvolt = <825000>;
79*4882a593Smuzhiyun		regulator-always-on;
80*4882a593Smuzhiyun		regulator-boot-on;
81*4882a593Smuzhiyun		regulator-settling-time-up-us = <250>;
82*4882a593Smuzhiyun		pwm-supply = <&vcc3v3_sys>;
83*4882a593Smuzhiyun		status = "okay";
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun	/*
87*4882a593Smuzhiyun	 * pwm1 is reserved as voltage adjustment in hardware
88*4882a593Smuzhiyun	 * use fixed regulator to avoid voltage adjustment by software
89*4882a593Smuzhiyun	 */
90*4882a593Smuzhiyun	vdd_logic_npu_vepu: vdd-logic-npu-vepu {
91*4882a593Smuzhiyun		compatible = "pwm-regulator";
92*4882a593Smuzhiyun		pwms = <&pwm1 0 5000 1>;
93*4882a593Smuzhiyun		regulator-name = "vdd_logic_npu_vepu";
94*4882a593Smuzhiyun		regulator-min-microvolt = <720000>;
95*4882a593Smuzhiyun		regulator-max-microvolt = <880000>;
96*4882a593Smuzhiyun		regulator-init-microvolt = <825000>;
97*4882a593Smuzhiyun		regulator-always-on;
98*4882a593Smuzhiyun		regulator-boot-on;
99*4882a593Smuzhiyun		regulator-settling-time-up-us = <250>;
100*4882a593Smuzhiyun		pwm-supply = <&vcc3v3_sys>;
101*4882a593Smuzhiyun		status = "okay";
102*4882a593Smuzhiyun	};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun	vdd_logic_npu_vepu_fixed: vdd-logic-npu-vepu-fixed {
105*4882a593Smuzhiyun		compatible = "regulator-fixed";
106*4882a593Smuzhiyun		regulator-name = "vdd_logic_npu_vepu-fixed";
107*4882a593Smuzhiyun		regulator-always-on;
108*4882a593Smuzhiyun		regulator-boot-on;
109*4882a593Smuzhiyun		regulator-min-microvolt = <825000>;
110*4882a593Smuzhiyun		regulator-max-microvolt = <825000>;
111*4882a593Smuzhiyun	};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
114*4882a593Smuzhiyun		compatible = "wlan-platdata";
115*4882a593Smuzhiyun		rockchip,grf = <&grf>;
116*4882a593Smuzhiyun		wifi_chip_type = "rtl8188fu";
117*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
118*4882a593Smuzhiyun		status = "okay";
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun&csi_dphy0 {
124*4882a593Smuzhiyun	status = "okay";
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun	ports {
127*4882a593Smuzhiyun		#address-cells = <1>;
128*4882a593Smuzhiyun		#size-cells = <0>;
129*4882a593Smuzhiyun		port@0 {
130*4882a593Smuzhiyun			reg = <0>;
131*4882a593Smuzhiyun			#address-cells = <1>;
132*4882a593Smuzhiyun			#size-cells = <0>;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
135*4882a593Smuzhiyun				reg = <1>;
136*4882a593Smuzhiyun				remote-endpoint = <&ucam_out0>;
137*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
138*4882a593Smuzhiyun			};
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun		port@1 {
141*4882a593Smuzhiyun			reg = <1>;
142*4882a593Smuzhiyun			#address-cells = <1>;
143*4882a593Smuzhiyun			#size-cells = <0>;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun			csidphy0_out: endpoint@0 {
146*4882a593Smuzhiyun				reg = <0>;
147*4882a593Smuzhiyun				remote-endpoint = <&isp_in>;
148*4882a593Smuzhiyun			};
149*4882a593Smuzhiyun		};
150*4882a593Smuzhiyun	};
151*4882a593Smuzhiyun};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun&gmac {
154*4882a593Smuzhiyun	phy-mode = "rmii";
155*4882a593Smuzhiyun	clock_in_out = "output";
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
158*4882a593Smuzhiyun	snps,reset-active-low;
159*4882a593Smuzhiyun	snps,reset-delays-us = <0 50000 50000>;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun	assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>;
162*4882a593Smuzhiyun	assigned-clock-parents = <&cru CLK_GMAC_SRC_M0>, <&cru RMII_MODE_CLK>;
163*4882a593Smuzhiyun	assigned-clock-rates = <50000000>;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun	pinctrl-names = "default";
166*4882a593Smuzhiyun	pinctrl-0 = <&rmiim0_miim &rgmiim0_rxer &rmiim0_bus2 &rgmiim0_mclkinout_level0>;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun	phy-handle = <&phy>;
169*4882a593Smuzhiyun	status = "okay";
170*4882a593Smuzhiyun};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun&i2c1 {
173*4882a593Smuzhiyun	status = "okay";
174*4882a593Smuzhiyun	clock-frequency = <400000>;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun	os04a10: os04a10@36 {
177*4882a593Smuzhiyun		compatible = "ovti,os04a10";
178*4882a593Smuzhiyun		reg = <0x36>;
179*4882a593Smuzhiyun		clocks = <&cru CLK_MIPICSI_OUT>;
180*4882a593Smuzhiyun		clock-names = "xvclk";
181*4882a593Smuzhiyun		power-domains = <&power RV1126_PD_VI>;
182*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default";
183*4882a593Smuzhiyun		pinctrl-0 = <&mipicsi_clk0>;
184*4882a593Smuzhiyun		avdd-supply = <&vcc3v3_sys>;
185*4882a593Smuzhiyun		dovdd-supply = <&vcc_1v8>;
186*4882a593Smuzhiyun		dvdd-supply = <&vcc_dvdd>;
187*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
188*4882a593Smuzhiyun		reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
189*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
190*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
191*4882a593Smuzhiyun		rockchip,camera-module-name = "CMK-OT1607-FV1";
192*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16";
193*4882a593Smuzhiyun		ir-cut = <&cam_ircut0>;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun		port {
196*4882a593Smuzhiyun			ucam_out0: endpoint {
197*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
198*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
199*4882a593Smuzhiyun			};
200*4882a593Smuzhiyun		};
201*4882a593Smuzhiyun	};
202*4882a593Smuzhiyun};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun&mdio {
205*4882a593Smuzhiyun	phy: phy@0 {
206*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
207*4882a593Smuzhiyun		reg = <0x0>;
208*4882a593Smuzhiyun	};
209*4882a593Smuzhiyun};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun&npu {
212*4882a593Smuzhiyun	npu-supply = <&vdd_logic_npu_vepu_fixed>;
213*4882a593Smuzhiyun};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun&pinctrl {
216*4882a593Smuzhiyun	ircut {
217*4882a593Smuzhiyun		/omit-if-no-ref/
218*4882a593Smuzhiyun		ircut_pins: ircut-pins {
219*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
220*4882a593Smuzhiyun					<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
221*4882a593Smuzhiyun		};
222*4882a593Smuzhiyun	};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun	sdmmc-pwr {
225*4882a593Smuzhiyun		/omit-if-no-ref/
226*4882a593Smuzhiyun		sdmmc_pwr: sdmmc-pwr {
227*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
228*4882a593Smuzhiyun		};
229*4882a593Smuzhiyun	};
230*4882a593Smuzhiyun};
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun&pmu_io_domains {
233*4882a593Smuzhiyun	status = "okay";
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun	pmuio0-supply = <&vcc3v3_sys>;
236*4882a593Smuzhiyun	pmuio1-supply = <&vcc3v3_sys>;
237*4882a593Smuzhiyun	vccio2-supply = <&vcc3v3_sys>;
238*4882a593Smuzhiyun	vccio4-supply = <&vcc_1v8>;
239*4882a593Smuzhiyun	vccio5-supply = <&vcc3v3_sys>;
240*4882a593Smuzhiyun	vccio6-supply = <&vcc3v3_sys>;
241*4882a593Smuzhiyun	vccio7-supply = <&vcc3v3_sys>;
242*4882a593Smuzhiyun};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun&rkisp_vir0 {
245*4882a593Smuzhiyun	status = "okay";
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun	ports {
248*4882a593Smuzhiyun		port@0 {
249*4882a593Smuzhiyun			reg = <0>;
250*4882a593Smuzhiyun			#address-cells = <1>;
251*4882a593Smuzhiyun			#size-cells = <0>;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun			isp_in: endpoint@0 {
254*4882a593Smuzhiyun				reg = <0>;
255*4882a593Smuzhiyun				remote-endpoint = <&csidphy0_out>;
256*4882a593Smuzhiyun			};
257*4882a593Smuzhiyun		};
258*4882a593Smuzhiyun	};
259*4882a593Smuzhiyun};
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun&rkvenc {
262*4882a593Smuzhiyun	venc-supply = <&vdd_logic_npu_vepu_fixed>;
263*4882a593Smuzhiyun};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun&rockchip_suspend {
266*4882a593Smuzhiyun	status = "okay";
267*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
268*4882a593Smuzhiyun	rockchip,sleep-mode-config = <
269*4882a593Smuzhiyun		(0
270*4882a593Smuzhiyun		| RKPM_SLP_ARMOFF
271*4882a593Smuzhiyun		| RKPM_SLP_PMU_PMUALIVE_32K
272*4882a593Smuzhiyun		| RKPM_SLP_PMU_DIS_OSC
273*4882a593Smuzhiyun		)
274*4882a593Smuzhiyun	>;
275*4882a593Smuzhiyun};
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun&sdmmc0_bus4 {
278*4882a593Smuzhiyun	rockchip,pins =
279*4882a593Smuzhiyun		/* sdmmc0_d0 */
280*4882a593Smuzhiyun		<1 RK_PA4 1 &pcfg_pull_up_drv_level_0>,
281*4882a593Smuzhiyun		/* sdmmc0_d1 */
282*4882a593Smuzhiyun		<1 RK_PA5 1 &pcfg_pull_up_drv_level_0>,
283*4882a593Smuzhiyun		/* sdmmc0_d2 */
284*4882a593Smuzhiyun		<1 RK_PA6 1 &pcfg_pull_up_drv_level_0>,
285*4882a593Smuzhiyun		/* sdmmc0_d3 */
286*4882a593Smuzhiyun		<1 RK_PA7 1 &pcfg_pull_up_drv_level_0>;
287*4882a593Smuzhiyun};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun&sdmmc0_clk {
290*4882a593Smuzhiyun	rockchip,pins =
291*4882a593Smuzhiyun		/* sdmmc0_clk */
292*4882a593Smuzhiyun		<1 RK_PB0 1 &pcfg_pull_up_drv_level_3>;
293*4882a593Smuzhiyun};
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun&sdmmc0_cmd {
296*4882a593Smuzhiyun	rockchip,pins =
297*4882a593Smuzhiyun		/* sdmmc0_cmd */
298*4882a593Smuzhiyun		<1 RK_PB1 1 &pcfg_pull_up_drv_level_0>;
299*4882a593Smuzhiyun};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun&sdmmc {
302*4882a593Smuzhiyun	bus-width = <4>;
303*4882a593Smuzhiyun	cap-mmc-highspeed;
304*4882a593Smuzhiyun	cap-sd-highspeed;
305*4882a593Smuzhiyun	card-detect-delay = <200>;
306*4882a593Smuzhiyun	rockchip,default-sample-phase = <90>;
307*4882a593Smuzhiyun	no-sdio;
308*4882a593Smuzhiyun	no-mmc;
309*4882a593Smuzhiyun	status = "okay";
310*4882a593Smuzhiyun	vmmc-supply = <&vcc_sd>;
311*4882a593Smuzhiyun};
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun&sfc {
314*4882a593Smuzhiyun	status = "okay";
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun	flash@0 {
317*4882a593Smuzhiyun		compatible = "spi-nand";
318*4882a593Smuzhiyun		reg = <0>;
319*4882a593Smuzhiyun		spi-max-frequency = <80000000>;
320*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
321*4882a593Smuzhiyun		spi-tx-bus-width = <1>;
322*4882a593Smuzhiyun	};
323*4882a593Smuzhiyun};
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun&u2phy_host {
326*4882a593Smuzhiyun	status = "okay";
327*4882a593Smuzhiyun};
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun&u2phy1 {
330*4882a593Smuzhiyun	status = "okay";
331*4882a593Smuzhiyun};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun&usb_host0_ehci {
334*4882a593Smuzhiyun	status = "okay";
335*4882a593Smuzhiyun};
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun&usb_host0_ohci {
338*4882a593Smuzhiyun	status = "okay";
339*4882a593Smuzhiyun};
340