1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 9*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 10*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 11*4882a593Smuzhiyun#include"rk3288-firefly.dtsi" 12*4882a593Smuzhiyun#include"rk3288-rkisp1.dtsi" 13*4882a593Smuzhiyun#include "rk3288-linux.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "Firefly-RK3288"; 17*4882a593Smuzhiyun compatible = "firefly,firefly-rk3288", "rockchip,rk3288"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /delete-node/ sdmmc-regulator; 20*4882a593Smuzhiyun vcc_sd: sdmmc-regulator { 21*4882a593Smuzhiyun compatible = "regulator-fixed"; 22*4882a593Smuzhiyun gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; 23*4882a593Smuzhiyun pinctrl-names = "default"; 24*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_pwr>; 25*4882a593Smuzhiyun regulator-name = "vcc_sd"; 26*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 27*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 28*4882a593Smuzhiyun startup-delay-us = <100000>; 29*4882a593Smuzhiyun vin-supply = <&vcc_io>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun vcc_lcd: vcc-lcd { 33*4882a593Smuzhiyun compatible = "regulator-fixed"; 34*4882a593Smuzhiyun regulator-boot-on; 35*4882a593Smuzhiyun enable-active-high; 36*4882a593Smuzhiyun pinctrl-names = "default"; 37*4882a593Smuzhiyun pinctrl-0 = <&lcd_en>; 38*4882a593Smuzhiyun regulator-name = "vcc_lcd"; 39*4882a593Smuzhiyun vin-supply = <&vcc_io>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun sound: sound { 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun compatible = "simple-audio-card"; 45*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 46*4882a593Smuzhiyun simple-audio-card,name = "rockchip,firefly-codec"; 47*4882a593Smuzhiyun simple-audio-card,mclk-fs = <512>; 48*4882a593Smuzhiyun simple-audio-card,widgets = 49*4882a593Smuzhiyun "Microphone", "Microphone Jack", 50*4882a593Smuzhiyun "Headphone", "Headphone Jack"; 51*4882a593Smuzhiyun simple-audio-card,routing = 52*4882a593Smuzhiyun "MIC1", "Microphone Jack", 53*4882a593Smuzhiyun "MIC2", "Microphone Jack", 54*4882a593Smuzhiyun "Microphone Jack", "micbias1", 55*4882a593Smuzhiyun "Headphone Jack", "HPOL", 56*4882a593Smuzhiyun "Headphone Jack", "HPOR"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun simple-audio-card,dai-link@0 { 59*4882a593Smuzhiyun format = "i2s"; 60*4882a593Smuzhiyun cpu { 61*4882a593Smuzhiyun sound-dai = <&i2s>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun codec { 65*4882a593Smuzhiyun sound-dai = <&es8323>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun simple-audio-card,dai-link@1 { 70*4882a593Smuzhiyun format = "i2s"; 71*4882a593Smuzhiyun cpu { 72*4882a593Smuzhiyun sound-dai = <&i2s>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun codec { 76*4882a593Smuzhiyun sound-dai = <&hdmi>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun spdif-sound { 82*4882a593Smuzhiyun status = "okay"; 83*4882a593Smuzhiyun compatible = "simple-audio-card"; 84*4882a593Smuzhiyun simple-audio-card,name = "ROCKCHIP,SPDIF"; 85*4882a593Smuzhiyun simple-audio-card,mclk-fs = <128>; 86*4882a593Smuzhiyun simple-audio-card,cpu { 87*4882a593Smuzhiyun sound-dai = <&spdif>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun simple-audio-card,codec { 90*4882a593Smuzhiyun sound-dai = <&spdif_out>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun backlight: backlight { 95*4882a593Smuzhiyun pwms = <&pwm1 0 1000000 0>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun hdmi_analog_sound: hdmi-analog-sound { 99*4882a593Smuzhiyun status = "disabled"; 100*4882a593Smuzhiyun rockchip,codec = <&es8323>, <&hdmi>; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun vccadc_ref: vccadc-ref { 104*4882a593Smuzhiyun compatible = "regulator-fixed"; 105*4882a593Smuzhiyun regulator-name = "vcc1v8_sys"; 106*4882a593Smuzhiyun regulator-always-on; 107*4882a593Smuzhiyun regulator-boot-on; 108*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 109*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from 114*4882a593Smuzhiyun * vcc_io directly. Those boards won't be able to power cycle SD cards 115*4882a593Smuzhiyun * but it shouldn't hurt to toggle this pin there anyway. 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun wireless-bluetooth { 119*4882a593Smuzhiyun clocks = <&hym8563>; 120*4882a593Smuzhiyun clock-names = "ext_clock"; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun ext_cam_clk: external-camera-clock { 124*4882a593Smuzhiyun compatible = "fixed-clock"; 125*4882a593Smuzhiyun clock-frequency = <27000000>; 126*4882a593Smuzhiyun clock-output-names = "CLK_CAMERA_27MHZ"; 127*4882a593Smuzhiyun #clock-cells = <0>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&ir{ 132*4882a593Smuzhiyun /delete-property/ pinctrl-0; 133*4882a593Smuzhiyun}; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun&hdmi { 136*4882a593Smuzhiyun #address-cells = <1>; 137*4882a593Smuzhiyun #size-cells = <0>; 138*4882a593Smuzhiyun #sound-dai-cells = <0>; 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun ports { 141*4882a593Smuzhiyun hdmi_in: port { 142*4882a593Smuzhiyun #address-cells = <1>; 143*4882a593Smuzhiyun #size-cells = <0>; 144*4882a593Smuzhiyun hdmi_in_vopb: endpoint@0 { 145*4882a593Smuzhiyun reg = <0>; 146*4882a593Smuzhiyun remote-endpoint = <&vopb_out_hdmi>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun hdmi_in_vopl: endpoint@1 { 149*4882a593Smuzhiyun reg = <1>; 150*4882a593Smuzhiyun remote-endpoint = <&vopl_out_hdmi>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun}; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun&hdmi_in_vopb { 157*4882a593Smuzhiyun status = "disabled"; 158*4882a593Smuzhiyun}; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun&hdmi_in_vopl { 161*4882a593Smuzhiyun status = "okay"; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&gmac { 165*4882a593Smuzhiyun snps,reset-gpio = <&gpio4 7 0>; 166*4882a593Smuzhiyun pinctrl-0 = <&rgmii_pins>; 167*4882a593Smuzhiyun max-speed = <100>; 168*4882a593Smuzhiyun status = "okay"; 169*4882a593Smuzhiyun}; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun&saradc { 172*4882a593Smuzhiyun vref-supply = <&vccadc_ref>; 173*4882a593Smuzhiyun status = "okay"; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&sdmmc { 177*4882a593Smuzhiyun sd-uhs-sdr12; 178*4882a593Smuzhiyun sd-uhs-sdr25; 179*4882a593Smuzhiyun sd-uhs-sdr50; 180*4882a593Smuzhiyun sd-uhs-sdr104; 181*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 182*4882a593Smuzhiyun status = "okay"; 183*4882a593Smuzhiyun}; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun&edp { 186*4882a593Smuzhiyun status = "disabled"; 187*4882a593Smuzhiyun}; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun&i2c0{ 190*4882a593Smuzhiyun /delete-node/ act8846@5a; 191*4882a593Smuzhiyun}; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun&i2c0 { 194*4882a593Smuzhiyun act8846: act8846@5a { 195*4882a593Smuzhiyun compatible = "active-semi,act8846"; 196*4882a593Smuzhiyun reg = <0x5a>; 197*4882a593Smuzhiyun pinctrl-names = "default"; 198*4882a593Smuzhiyun pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; 199*4882a593Smuzhiyun system-power-controller; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun vp1-supply = <&vcc_sys>; 202*4882a593Smuzhiyun vp2-supply = <&vcc_sys>; 203*4882a593Smuzhiyun vp3-supply = <&vcc_sys>; 204*4882a593Smuzhiyun vp4-supply = <&vcc_sys>; 205*4882a593Smuzhiyun inl1-supply = <&vcc_sys>; 206*4882a593Smuzhiyun inl2-supply = <&vcc_sys>; 207*4882a593Smuzhiyun inl3-supply = <&vcc_20>; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun regulators { 210*4882a593Smuzhiyun vcc_ddr: REG1 { 211*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 212*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 213*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 214*4882a593Smuzhiyun regulator-always-on; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun vcc_io: REG2 { 218*4882a593Smuzhiyun regulator-name = "vcc_io"; 219*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 220*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 221*4882a593Smuzhiyun regulator-always-on; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun vdd_log: REG3 { 225*4882a593Smuzhiyun regulator-name = "vdd_log"; 226*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 227*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 228*4882a593Smuzhiyun regulator-always-on; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun vcc_20: REG4 { 232*4882a593Smuzhiyun regulator-name = "vcc_20"; 233*4882a593Smuzhiyun regulator-min-microvolt = <2000000>; 234*4882a593Smuzhiyun regulator-max-microvolt = <2000000>; 235*4882a593Smuzhiyun regulator-always-on; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun vccio_sd: REG5 { 239*4882a593Smuzhiyun regulator-name = "vccio_sd"; 240*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 241*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 242*4882a593Smuzhiyun regulator-always-on; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun vdd10_lcd: REG6 { 246*4882a593Smuzhiyun regulator-name = "vdd10_lcd"; 247*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 248*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 249*4882a593Smuzhiyun regulator-always-on; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun vcca_33: REG7 { 253*4882a593Smuzhiyun regulator-name = "vcca_33"; 254*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 255*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 256*4882a593Smuzhiyun regulator-always-on; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun vcc_lan: REG8 { 260*4882a593Smuzhiyun regulator-name = "vcc_lan"; 261*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 262*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 263*4882a593Smuzhiyun regulator-always-on; 264*4882a593Smuzhiyun regulator-boot-on; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun vcc_pmu: REG9 { 268*4882a593Smuzhiyun regulator-name = "vcc_pmu"; 269*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 270*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 271*4882a593Smuzhiyun regulator-always-on; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun vdd_10: REG10 { 275*4882a593Smuzhiyun regulator-name = "vdd_10"; 276*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 277*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 278*4882a593Smuzhiyun regulator-always-on; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun vccio_wl: vcc_18: REG11 { 282*4882a593Smuzhiyun regulator-name = "vcc_18"; 283*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 284*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 285*4882a593Smuzhiyun regulator-always-on; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun vcc18_lcd: REG12 { 289*4882a593Smuzhiyun regulator-name = "vcc18_lcd"; 290*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 291*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 292*4882a593Smuzhiyun regulator-always-on; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun}; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun&i2c1 { 299*4882a593Smuzhiyun status = "okay"; 300*4882a593Smuzhiyun clock-frequency = <400000>; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun camera: tc358749@0f { 303*4882a593Smuzhiyun compatible = "toshiba,tc358749"; 304*4882a593Smuzhiyun reg = <0x0f>; 305*4882a593Smuzhiyun clocks = <&ext_cam_clk>; 306*4882a593Smuzhiyun clock-names = "refclk"; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun pinctrl-names = "default"; 309*4882a593Smuzhiyun pinctrl-0 = <&hdmiin_gpios>; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun reset-gpios = <&gpio8 8 GPIO_ACTIVE_LOW>; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun interrupt-parent = <&gpio8>; 314*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun port { 317*4882a593Smuzhiyun camera_out: endpoint { 318*4882a593Smuzhiyun remote-endpoint = <&mipi_rx0_in>; 319*4882a593Smuzhiyun clock-lanes = <0>; 320*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 321*4882a593Smuzhiyun clock-noncontinuous; 322*4882a593Smuzhiyun link-frequencies = 323*4882a593Smuzhiyun /bits/ 64 <297000000>; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun}; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun&i2c2 { 330*4882a593Smuzhiyun status = "okay"; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun es8323: es8323@10 { 333*4882a593Smuzhiyun status = "okay"; 334*4882a593Smuzhiyun compatible = "everest,es8323"; 335*4882a593Smuzhiyun reg = <0x10>; 336*4882a593Smuzhiyun spk-con-gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>; 337*4882a593Smuzhiyun hp-det-gpio = <&gpio7 15 GPIO_ACTIVE_LOW>; 338*4882a593Smuzhiyun clock-names = "mclk"; 339*4882a593Smuzhiyun clocks = <&cru SCLK_I2S0_OUT>; 340*4882a593Smuzhiyun pinctrl-names = "default"; 341*4882a593Smuzhiyun pinctrl-0 = <&i2s0_mclk>; 342*4882a593Smuzhiyun #sound-dai-cells = <0>; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun}; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun&i2c3 { 347*4882a593Smuzhiyun status = "okay"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun&i2c4 { 351*4882a593Smuzhiyun status = "okay"; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&i2s { 355*4882a593Smuzhiyun #sound-dai-cells = <0>; 356*4882a593Smuzhiyun status = "okay"; 357*4882a593Smuzhiyun}; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun&pwm1 { 360*4882a593Smuzhiyun status = "okay"; 361*4882a593Smuzhiyun}; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun&isp { 364*4882a593Smuzhiyun status = "okay"; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun port { 367*4882a593Smuzhiyun isp_mipi_in: endpoint { 368*4882a593Smuzhiyun remote-endpoint = <&dphy_rx0_out>; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun}; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun&isp_mmu { 374*4882a593Smuzhiyun status = "okay"; 375*4882a593Smuzhiyun}; 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun&mipi_phy_rx0 { 378*4882a593Smuzhiyun status = "okay"; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun ports { 381*4882a593Smuzhiyun #address-cells = <1>; 382*4882a593Smuzhiyun #size-cells = <0>; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun port@0 { 385*4882a593Smuzhiyun reg = <0>; 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun mipi_rx0_in: endpoint { 388*4882a593Smuzhiyun remote-endpoint = <&camera_out>; 389*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun port@1 { 394*4882a593Smuzhiyun reg = <1>; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun dphy_rx0_out: endpoint { 397*4882a593Smuzhiyun remote-endpoint = <&isp_mipi_in>; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun }; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun}; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun&vopb { 404*4882a593Smuzhiyun status = "okay"; 405*4882a593Smuzhiyun vopb_out: port { 406*4882a593Smuzhiyun vopb_out_edp: endpoint@1 { 407*4882a593Smuzhiyun reg = <1>; 408*4882a593Smuzhiyun remote-endpoint = <&edp_in_vopb>; 409*4882a593Smuzhiyun }; 410*4882a593Smuzhiyun }; 411*4882a593Smuzhiyun}; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun&vopl { 414*4882a593Smuzhiyun status = "okay"; 415*4882a593Smuzhiyun vopl_out: port { 416*4882a593Smuzhiyun #address-cells = <1>; 417*4882a593Smuzhiyun #size-cells = <0>; 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun vopl_out_hdmi: endpoint@0 { 420*4882a593Smuzhiyun reg = <0>; 421*4882a593Smuzhiyun remote-endpoint = <&hdmi_in_vopl>; 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun }; 424*4882a593Smuzhiyun}; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun&rga { 427*4882a593Smuzhiyun status = "okay"; 428*4882a593Smuzhiyun}; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun&tsadc { 431*4882a593Smuzhiyun rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 432*4882a593Smuzhiyun}; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun&pinctrl { 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun /* sata:gpio0 c1 */ 437*4882a593Smuzhiyun init-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun pcfg_output_high: pcfg-output-high { 440*4882a593Smuzhiyun output-high; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun pcfg_output_low: pcfg-output-low { 444*4882a593Smuzhiyun output-low; 445*4882a593Smuzhiyun }; 446*4882a593Smuzhiyun pmic { 447*4882a593Smuzhiyun pmic_int: pmic-int { 448*4882a593Smuzhiyun rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 449*4882a593Smuzhiyun }; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun lcd { 453*4882a593Smuzhiyun lcd_cs: lcd-cs { 454*4882a593Smuzhiyun rockchip,pins = <7 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 455*4882a593Smuzhiyun }; 456*4882a593Smuzhiyun 457*4882a593Smuzhiyun lcd_en: lcd-en { 458*4882a593Smuzhiyun rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun act8846 { 463*4882a593Smuzhiyun pmic_vsel: pmic-vsel { 464*4882a593Smuzhiyun rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_output_low>; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun pwr_hold: pwr-hold { 468*4882a593Smuzhiyun rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun backlight { 473*4882a593Smuzhiyun bl_en: bl-en { 474*4882a593Smuzhiyun rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun }; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun buttons { 479*4882a593Smuzhiyun pwrbtn: pwrbtn { 480*4882a593Smuzhiyun rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 481*4882a593Smuzhiyun }; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun hdmiin { 485*4882a593Smuzhiyun hdmiin_gpios: hdmiin_gpios { 486*4882a593Smuzhiyun rockchip,pins = 487*4882a593Smuzhiyun <7 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>, 488*4882a593Smuzhiyun <7 RK_PC5 RK_FUNC_GPIO &pcfg_output_high>, 489*4882a593Smuzhiyun <8 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, 490*4882a593Smuzhiyun <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun }; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun i2c1 { 495*4882a593Smuzhiyun i2c1_xfer: i2c1-xfer { 496*4882a593Smuzhiyun rockchip,pins = <8 RK_PA4 1 &pcfg_pull_up>, 497*4882a593Smuzhiyun <8 RK_PA5 1 &pcfg_pull_up>; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun}; 501