xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/rk3288-evb-rk628-rgb2lvds-avb.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun/dts-v1/;
5*4882a593Smuzhiyun#include "rk3288-evb-rk628.dtsi"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/ {
8*4882a593Smuzhiyun	model = "Rockchip RK3288 EVB RK628 Board";
9*4882a593Smuzhiyun	compatible = "rockchip,rk3288-evb-rk628", "rockchip,rk3288";
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun	panel {
12*4882a593Smuzhiyun		compatible = "simple-panel";
13*4882a593Smuzhiyun		backlight = <&backlight>;
14*4882a593Smuzhiyun		enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
15*4882a593Smuzhiyun		prepare-delay-ms = <20>;
16*4882a593Smuzhiyun		enable-delay-ms = <20>;
17*4882a593Smuzhiyun		disable-delay-ms = <20>;
18*4882a593Smuzhiyun		unprepare-delay-ms = <20>;
19*4882a593Smuzhiyun		bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		display-timings {
22*4882a593Smuzhiyun			native-mode = <&timing0>;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun			timing0: timing0 {
25*4882a593Smuzhiyun				clock-frequency = <48000000>;
26*4882a593Smuzhiyun				hactive = <1024>;
27*4882a593Smuzhiyun				vactive = <600>;
28*4882a593Smuzhiyun				hback-porch = <90>;
29*4882a593Smuzhiyun				hfront-porch = <90>;
30*4882a593Smuzhiyun				vback-porch = <10>;
31*4882a593Smuzhiyun				vfront-porch = <10>;
32*4882a593Smuzhiyun				hsync-len = <90>;
33*4882a593Smuzhiyun				vsync-len = <10>;
34*4882a593Smuzhiyun				hsync-active = <0>;
35*4882a593Smuzhiyun				vsync-active = <0>;
36*4882a593Smuzhiyun				de-active = <0>;
37*4882a593Smuzhiyun				pixelclk-active = <0>;
38*4882a593Smuzhiyun			};
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun		port {
42*4882a593Smuzhiyun			panel_in_lvds: endpoint {
43*4882a593Smuzhiyun				remote-endpoint = <&lvds_out_panel>;
44*4882a593Smuzhiyun			};
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun&rk628_lvds {
50*4882a593Smuzhiyun	status = "okay";
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	ports {
53*4882a593Smuzhiyun		#address-cells = <1>;
54*4882a593Smuzhiyun		#size-cells = <0>;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun		port@0 {
57*4882a593Smuzhiyun			reg = <0>;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun			lvds_in_post_process: endpoint {
60*4882a593Smuzhiyun				remote-endpoint = <&post_process_out_lvds>;
61*4882a593Smuzhiyun			};
62*4882a593Smuzhiyun		};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun		port@1 {
65*4882a593Smuzhiyun			reg = <1>;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun			lvds_out_panel: endpoint {
68*4882a593Smuzhiyun				remote-endpoint = <&panel_in_lvds>;
69*4882a593Smuzhiyun			};
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun&rk628_combtxphy {
75*4882a593Smuzhiyun	status = "okay";
76*4882a593Smuzhiyun};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun&rk628_post_process {
79*4882a593Smuzhiyun	pinctrl-names = "default";
80*4882a593Smuzhiyun	pinctrl-0 = <&rk628_vop_pins>;
81*4882a593Smuzhiyun	status = "okay";
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	ports {
84*4882a593Smuzhiyun		#address-cells = <1>;
85*4882a593Smuzhiyun		#size-cells = <0>;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		port@0 {
88*4882a593Smuzhiyun			reg = <0>;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun			post_process_in_rgb: endpoint {
91*4882a593Smuzhiyun				remote-endpoint = <&rgb_out_post_process>;
92*4882a593Smuzhiyun			};
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun		port@1 {
96*4882a593Smuzhiyun			reg = <1>;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun			post_process_out_lvds: endpoint {
99*4882a593Smuzhiyun				remote-endpoint = <&lvds_in_post_process>;
100*4882a593Smuzhiyun			};
101*4882a593Smuzhiyun		};
102*4882a593Smuzhiyun	};
103*4882a593Smuzhiyun};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun&rgb {
106*4882a593Smuzhiyun	status = "okay";
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	ports {
109*4882a593Smuzhiyun		port@1 {
110*4882a593Smuzhiyun			reg = <1>;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun			rgb_out_post_process: endpoint {
113*4882a593Smuzhiyun				remote-endpoint = <&post_process_in_rgb>;
114*4882a593Smuzhiyun			};
115*4882a593Smuzhiyun		};
116*4882a593Smuzhiyun	};
117*4882a593Smuzhiyun};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun&video_phy {
120*4882a593Smuzhiyun	status = "okay";
121*4882a593Smuzhiyun};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun&rgb_in_vopb {
124*4882a593Smuzhiyun	status = "disabled";
125*4882a593Smuzhiyun};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun&rgb_in_vopl {
128*4882a593Smuzhiyun	status = "okay";
129*4882a593Smuzhiyun};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun&route_rgb {
132*4882a593Smuzhiyun	connect = <&vopl_out_rgb>;
133*4882a593Smuzhiyun	status = "disabled";
134*4882a593Smuzhiyun};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun&vopb {
137*4882a593Smuzhiyun	assigned-clocks = <&cru DCLK_VOP0>;
138*4882a593Smuzhiyun	assigned-clock-parents = <&cru PLL_GPLL>;
139*4882a593Smuzhiyun};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun&vopl {
142*4882a593Smuzhiyun	assigned-clocks = <&cru DCLK_VOP1>;
143*4882a593Smuzhiyun	assigned-clock-parents = <&cru PLL_CPLL>;
144*4882a593Smuzhiyun};
145