1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/dts-v1/; 5*4882a593Smuzhiyun#include "rk3288-evb-rk628.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun&sound { 8*4882a593Smuzhiyun status = "okay"; 9*4882a593Smuzhiyun}; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun&rk628_hdmi { 12*4882a593Smuzhiyun status = "okay"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun ports { 15*4882a593Smuzhiyun #address-cells = <1>; 16*4882a593Smuzhiyun #size-cells = <0>; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun port@0 { 19*4882a593Smuzhiyun reg = <0>; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun hdmi_in_post_process: endpoint { 22*4882a593Smuzhiyun remote-endpoint = <&post_process_out_hdmi>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun&rk628_post_process { 29*4882a593Smuzhiyun pinctrl-names = "default"; 30*4882a593Smuzhiyun pinctrl-0 = <&rk628_vop_pins>; 31*4882a593Smuzhiyun status = "okay"; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun ports { 34*4882a593Smuzhiyun #address-cells = <1>; 35*4882a593Smuzhiyun #size-cells = <0>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun port@0 { 38*4882a593Smuzhiyun reg = <0>; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun post_process_in_rgb: endpoint { 41*4882a593Smuzhiyun remote-endpoint = <&rgb_out_post_process>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun port@1 { 46*4882a593Smuzhiyun reg = <1>; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun post_process_out_hdmi: endpoint { 49*4882a593Smuzhiyun remote-endpoint = <&hdmi_in_post_process>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun&rgb { 56*4882a593Smuzhiyun status = "okay"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun ports { 59*4882a593Smuzhiyun port@1 { 60*4882a593Smuzhiyun reg = <1>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun rgb_out_post_process: endpoint { 63*4882a593Smuzhiyun remote-endpoint = <&post_process_in_rgb>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&video_phy { 71*4882a593Smuzhiyun status = "okay"; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&rgb_in_vopb { 75*4882a593Smuzhiyun status = "disabled"; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&rgb_in_vopl { 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&route_rgb { 83*4882a593Smuzhiyun connect = <&vopl_out_rgb>; 84*4882a593Smuzhiyun status = "disabled"; 85*4882a593Smuzhiyun}; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun&vopb { 88*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP0>; 89*4882a593Smuzhiyun assigned-clock-parents = <&cru PLL_CPLL>; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&vopl { 93*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP1>; 94*4882a593Smuzhiyun assigned-clock-parents = <&cru PLL_GPLL>; 95*4882a593Smuzhiyun}; 96