1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/clock/rockchip-ddr.h> 8*4882a593Smuzhiyun#include <dt-bindings/dram/rockchip,rk322x.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun dram_timing: dram_timing { 12*4882a593Smuzhiyun compatible = "rockchip,dram-timing"; 13*4882a593Smuzhiyun dram_spd_bin = <DDR3_DEFAULT>; 14*4882a593Smuzhiyun sr_idle = <0x18>; 15*4882a593Smuzhiyun pd_idle = <0x20>; 16*4882a593Smuzhiyun dram_dll_disb_freq = <300>; 17*4882a593Smuzhiyun phy_dll_disb_freq = <400>; 18*4882a593Smuzhiyun dram_odt_disb_freq = <333>; 19*4882a593Smuzhiyun phy_odt_disb_freq = <333>; 20*4882a593Smuzhiyun ddr3_drv = <DDR3_DS_40ohm>; 21*4882a593Smuzhiyun ddr3_odt = <DDR3_ODT_120ohm>; 22*4882a593Smuzhiyun lpddr3_drv = <LP3_DS_34ohm>; 23*4882a593Smuzhiyun lpddr3_odt = <LP3_ODT_240ohm>; 24*4882a593Smuzhiyun lpddr2_drv = <LP2_DS_34ohm>; 25*4882a593Smuzhiyun /* lpddr2 not supported odt */ 26*4882a593Smuzhiyun phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_45ohm>; 27*4882a593Smuzhiyun phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_45ohm>; 28*4882a593Smuzhiyun phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_34ohm>; 29*4882a593Smuzhiyun phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>; 30*4882a593Smuzhiyun phy_lp23_clk_drv = <PHY_LP23_RON_RTT_43ohm>; 31*4882a593Smuzhiyun phy_lp23_cmd_drv = <PHY_LP23_RON_RTT_34ohm>; 32*4882a593Smuzhiyun phy_lp23_dqs_drv = <PHY_LP23_RON_RTT_34ohm>; 33*4882a593Smuzhiyun phy_lp3_odt = <PHY_LP23_RON_RTT_240ohm>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun}; 36