1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 10*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 11*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 12*4882a593Smuzhiyun#include "rk3126.dtsi" 13*4882a593Smuzhiyun#include "rk312x-android.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun adc-keys { 17*4882a593Smuzhiyun compatible = "adc-keys"; 18*4882a593Smuzhiyun io-channels = <&saradc 2>; 19*4882a593Smuzhiyun io-channel-names = "buttons"; 20*4882a593Smuzhiyun poll-interval = <100>; 21*4882a593Smuzhiyun keyup-threshold-microvolt = <3300000>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun button-up { 24*4882a593Smuzhiyun label = "Volume Up"; 25*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 26*4882a593Smuzhiyun press-threshold-microvolt = <0>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun button-down { 30*4882a593Smuzhiyun label = "Volume Down"; 31*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 32*4882a593Smuzhiyun press-threshold-microvolt = <1650000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun backlight: backlight { 37*4882a593Smuzhiyun compatible = "pwm-backlight"; 38*4882a593Smuzhiyun pwms = <&pwm0 0 25000 0>; 39*4882a593Smuzhiyun brightness-levels = < 40*4882a593Smuzhiyun 255 169 168 168 167 166 166 165 41*4882a593Smuzhiyun 164 164 163 162 162 161 160 160 42*4882a593Smuzhiyun 159 158 158 157 156 156 155 154 43*4882a593Smuzhiyun 154 153 152 152 151 150 150 149 44*4882a593Smuzhiyun 148 148 147 146 146 145 144 144 45*4882a593Smuzhiyun 143 142 142 141 140 140 139 138 46*4882a593Smuzhiyun 138 137 136 136 135 134 134 133 47*4882a593Smuzhiyun 132 132 131 130 130 129 128 128 48*4882a593Smuzhiyun 127 126 126 125 124 124 123 122 49*4882a593Smuzhiyun 122 121 120 120 119 118 118 117 50*4882a593Smuzhiyun 116 116 115 114 114 113 112 112 51*4882a593Smuzhiyun 111 110 110 109 108 108 107 106 52*4882a593Smuzhiyun 106 105 104 104 103 102 102 101 53*4882a593Smuzhiyun 100 100 99 98 98 97 96 96 54*4882a593Smuzhiyun 95 94 94 93 92 92 91 90 55*4882a593Smuzhiyun 90 89 88 88 87 86 86 85 56*4882a593Smuzhiyun 84 84 83 82 82 81 80 80 57*4882a593Smuzhiyun 79 78 78 77 76 76 75 74 58*4882a593Smuzhiyun 74 73 72 72 71 70 70 69 59*4882a593Smuzhiyun 68 68 67 66 66 65 64 64 60*4882a593Smuzhiyun 63 62 62 61 60 60 59 58 61*4882a593Smuzhiyun 58 57 56 56 55 54 54 53 62*4882a593Smuzhiyun 52 52 51 50 50 49 48 48 63*4882a593Smuzhiyun 47 46 46 45 44 44 43 42 64*4882a593Smuzhiyun 42 41 40 40 39 38 38 37 65*4882a593Smuzhiyun 36 36 35 34 34 33 32 32 66*4882a593Smuzhiyun 31 30 30 29 28 28 27 26 67*4882a593Smuzhiyun 26 25 24 24 23 22 22 21 68*4882a593Smuzhiyun 20 20 19 18 18 17 16 16 69*4882a593Smuzhiyun 15 14 14 13 12 12 11 10 70*4882a593Smuzhiyun 10 9 8 8 7 6 6 5 71*4882a593Smuzhiyun 4 4 3 2 1 1 1 0>; 72*4882a593Smuzhiyun default-brightness-level = <128>; 73*4882a593Smuzhiyun enable-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun charge-animation { 77*4882a593Smuzhiyun compatible = "rockchip,uboot-charge"; 78*4882a593Smuzhiyun rockchip,uboot-charge-on = <1>; 79*4882a593Smuzhiyun rockchip,android-charge-on = <0>; 80*4882a593Smuzhiyun rockchip,uboot-low-power-voltage = <3500>; 81*4882a593Smuzhiyun rockchip,screen-on-voltage = <3600>; 82*4882a593Smuzhiyun status = "okay"; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun rockchip_headset { 86*4882a593Smuzhiyun compatible = "rockchip_headset"; 87*4882a593Smuzhiyun headset_gpio = <&gpio2 18 GPIO_ACTIVE_LOW>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun sound { 91*4882a593Smuzhiyun compatible = "simple-audio-card"; 92*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 93*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 94*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rk312x"; 95*4882a593Smuzhiyun simple-audio-card,cpu { 96*4882a593Smuzhiyun sound-dai = <&i2s_2ch>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun simple-audio-card,codec { 99*4882a593Smuzhiyun sound-dai = <&codec>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun vccadc_ref: vccadc-ref { 104*4882a593Smuzhiyun compatible = "regulator-fixed"; 105*4882a593Smuzhiyun regulator-name = "SARADC_AVDD33"; 106*4882a593Smuzhiyun regulator-always-on; 107*4882a593Smuzhiyun regulator-boot-on; 108*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 109*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun vcc_sys: vcc-sys { 113*4882a593Smuzhiyun compatible = "regulator-fixed"; 114*4882a593Smuzhiyun regulator-name = "vcc_sys"; 115*4882a593Smuzhiyun regulator-min-microvolt = <4000000>; 116*4882a593Smuzhiyun regulator-max-microvolt = <4000000>; 117*4882a593Smuzhiyun regulator-always-on; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun xin32k: xin32k { 121*4882a593Smuzhiyun compatible = "fixed-clock"; 122*4882a593Smuzhiyun clock-frequency = <32768>; 123*4882a593Smuzhiyun clock-output-names = "xin32k"; 124*4882a593Smuzhiyun #clock-cells = <0>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun wireless-bluetooth { 128*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 129*4882a593Smuzhiyun /* wifi-bt-power-toggle; */ 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun keep_wifi_power_on = <1>; 132*4882a593Smuzhiyun uart_rts_gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO1_B3 */ 133*4882a593Smuzhiyun pinctrl-names = "default","rts_gpio"; 134*4882a593Smuzhiyun pinctrl-0 = <&uart1_rts>; 135*4882a593Smuzhiyun pinctrl-1 = <&uart1_rts_gpio>; 136*4882a593Smuzhiyun BT,reset_gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; /* GPIO2_B1 */ 137*4882a593Smuzhiyun BT,wake_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; /* GPIO0_D3 */ 138*4882a593Smuzhiyun BT,wake_host_irq = <&gpio2 21 GPIO_ACTIVE_LOW>; /* GPIO2_C5 */ 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun wireless-wlan { 143*4882a593Smuzhiyun compatible = "wlan-platdata"; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun wifi_chip_type = "rtl8723cs"; 146*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio2 13 GPIO_ACTIVE_HIGH>; 147*4882a593Smuzhiyun status = "okay"; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun}; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun&codec { 152*4882a593Smuzhiyun #sound-dai-cells = <0>; 153*4882a593Smuzhiyun hp-ctl-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; 154*4882a593Smuzhiyun spk-ctl-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 155*4882a593Smuzhiyun spk-mute-delay = <200>; 156*4882a593Smuzhiyun hp-mute-delay = <100>; 157*4882a593Smuzhiyun is_rk3128 = <0>; 158*4882a593Smuzhiyun spk_volume = <25>; 159*4882a593Smuzhiyun hp_volume = <25>; 160*4882a593Smuzhiyun capture_volume = <26>; 161*4882a593Smuzhiyun gpio_debug = <1>; 162*4882a593Smuzhiyun codec_hp_det = <0>; 163*4882a593Smuzhiyun status = "okay"; 164*4882a593Smuzhiyun}; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun&cif_new { 167*4882a593Smuzhiyun status = "okay"; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun ports { 170*4882a593Smuzhiyun port@0 { 171*4882a593Smuzhiyun cif_in_fcam: endpoint@0 { 172*4882a593Smuzhiyun remote-endpoint = <&gc0329_out>; 173*4882a593Smuzhiyun vsync-active = <1>; 174*4882a593Smuzhiyun hsync-active = <1>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun cif_in_bcam: endpoint@1 { 178*4882a593Smuzhiyun remote-endpoint = <&gc2145_out>; 179*4882a593Smuzhiyun vsync-active = <0>; 180*4882a593Smuzhiyun hsync-active = <1>; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun}; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun&cpu0 { 187*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 188*4882a593Smuzhiyun}; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun&dsi { 191*4882a593Smuzhiyun status = "okay"; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun panel@0 { 194*4882a593Smuzhiyun compatible = "fc,fy07018dh26d372-d", "simple-panel-dsi"; 195*4882a593Smuzhiyun reg = <0>; 196*4882a593Smuzhiyun backlight = <&backlight>; 197*4882a593Smuzhiyun power-supply = <&ldo6>; 198*4882a593Smuzhiyun power-invert; 199*4882a593Smuzhiyun enable-gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; 200*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>; 201*4882a593Smuzhiyun prepare-delay-ms = <20>; 202*4882a593Smuzhiyun reset-delay-ms = <20>; 203*4882a593Smuzhiyun init-delay-ms = <20>; 204*4882a593Smuzhiyun enable-delay-ms = <120>; 205*4882a593Smuzhiyun disable-delay-ms = <20>; 206*4882a593Smuzhiyun unprepare-delay-ms = <20>; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun width-mm = <153>; 209*4882a593Smuzhiyun height-mm = <85>; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 212*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 213*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 214*4882a593Smuzhiyun dsi,lanes = <4>; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun panel-init-sequence = [ 217*4882a593Smuzhiyun 05 1e 01 01 218*4882a593Smuzhiyun 15 00 02 80 47 219*4882a593Smuzhiyun 15 00 02 81 40 220*4882a593Smuzhiyun 15 00 02 82 04 221*4882a593Smuzhiyun 15 00 02 83 77 222*4882a593Smuzhiyun 15 00 02 84 0f 223*4882a593Smuzhiyun 15 00 02 85 70 224*4882a593Smuzhiyun 15 78 02 86 70 225*4882a593Smuzhiyun ]; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun display-timings { 228*4882a593Smuzhiyun native-mode = <&timing0>; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun timing0: timing0 { 231*4882a593Smuzhiyun clock-frequency = <49500000>; 232*4882a593Smuzhiyun hactive = <1024>; 233*4882a593Smuzhiyun hfront-porch = <120>; 234*4882a593Smuzhiyun hsync-len = <40>; 235*4882a593Smuzhiyun hback-porch = <120>; 236*4882a593Smuzhiyun vactive = <600>; 237*4882a593Smuzhiyun vfront-porch = <14>; 238*4882a593Smuzhiyun vsync-len = <4>; 239*4882a593Smuzhiyun vback-porch = <14>; 240*4882a593Smuzhiyun hsync-active = <0>; 241*4882a593Smuzhiyun vsync-active = <0>; 242*4882a593Smuzhiyun de-active = <0>; 243*4882a593Smuzhiyun pixelclk-active = <0>; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun ports { 248*4882a593Smuzhiyun #address-cells = <1>; 249*4882a593Smuzhiyun #size-cells = <0>; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun port@0 { 252*4882a593Smuzhiyun reg = <0>; 253*4882a593Smuzhiyun panel_in_dsi: endpoint { 254*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun ports { 261*4882a593Smuzhiyun #address-cells = <1>; 262*4882a593Smuzhiyun #size-cells = <0>; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun port@1 { 265*4882a593Smuzhiyun reg = <1>; 266*4882a593Smuzhiyun dsi_out_panel: endpoint { 267*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun}; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun&route_dsi { 274*4882a593Smuzhiyun status = "okay"; 275*4882a593Smuzhiyun}; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun&dmc { 278*4882a593Smuzhiyun center-supply = <&vdd_log>; 279*4882a593Smuzhiyun}; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun&emmc { 282*4882a593Smuzhiyun bus-width = <8>; 283*4882a593Smuzhiyun cap-mmc-highspeed; 284*4882a593Smuzhiyun no-sdio; 285*4882a593Smuzhiyun no-sd; 286*4882a593Smuzhiyun disable-wp; 287*4882a593Smuzhiyun non-removable; 288*4882a593Smuzhiyun num-slots = <1>; 289*4882a593Smuzhiyun status = "okay"; 290*4882a593Smuzhiyun}; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun&gpu { 293*4882a593Smuzhiyun status = "okay"; 294*4882a593Smuzhiyun mali-supply = <&vdd_log>; 295*4882a593Smuzhiyun}; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun&i2c0 { 298*4882a593Smuzhiyun status = "okay"; 299*4882a593Smuzhiyun clock-frequency = <400000>; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun gc0329@31 { 302*4882a593Smuzhiyun compatible = "galaxycore,gc0329"; 303*4882a593Smuzhiyun reg = <0x31>; 304*4882a593Smuzhiyun pinctrl-names = "default"; 305*4882a593Smuzhiyun pinctrl-0 = <&fcam_pd>; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 308*4882a593Smuzhiyun clock-names = "xvclk"; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun avdd-supply = <&vcc28_cif>; 311*4882a593Smuzhiyun dovdd-supply = <&vcc18_cif>; 312*4882a593Smuzhiyun dvdd-supply = <&vcc18_cif>; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun pwdn-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; 315*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 316*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 317*4882a593Smuzhiyun rockchip,camera-module-name = "default"; 318*4882a593Smuzhiyun rockchip,camera-module-lens-name = "default"; 319*4882a593Smuzhiyun port { 320*4882a593Smuzhiyun gc0329_out: endpoint { 321*4882a593Smuzhiyun remote-endpoint = <&cif_in_fcam>; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun gc2145@3c { 327*4882a593Smuzhiyun compatible = "galaxycore,gc2145"; 328*4882a593Smuzhiyun reg = <0x3c>; 329*4882a593Smuzhiyun pinctrl-names = "default"; 330*4882a593Smuzhiyun pinctrl-0 = <&bcam_pd>; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 333*4882a593Smuzhiyun clock-names = "xvclk"; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun avdd-supply = <&vcc28_cif>; 336*4882a593Smuzhiyun dovdd-supply = <&vcc18_cif>; 337*4882a593Smuzhiyun dvdd-supply = <&vcc18_cif>; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun pwdn-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 340*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 341*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 342*4882a593Smuzhiyun rockchip,camera-module-name = "default"; 343*4882a593Smuzhiyun rockchip,camera-module-lens-name = "default"; 344*4882a593Smuzhiyun port { 345*4882a593Smuzhiyun gc2145_out: endpoint { 346*4882a593Smuzhiyun remote-endpoint = <&cif_in_bcam>; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun }; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun ts@40 { 352*4882a593Smuzhiyun compatible = "gslX680-d708"; 353*4882a593Smuzhiyun reg = <0x40>; 354*4882a593Smuzhiyun touch-gpio = <&gpio2 20 IRQ_TYPE_LEVEL_LOW>; 355*4882a593Smuzhiyun wake-gpio = <&gpio2 12 IRQ_TYPE_LEVEL_LOW>; 356*4882a593Smuzhiyun screen_max_x = <800>; 357*4882a593Smuzhiyun screen_max_y = <480>; 358*4882a593Smuzhiyun status = "okay"; 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun rk816: pmic@1a { 362*4882a593Smuzhiyun compatible = "rockchip,rk816"; 363*4882a593Smuzhiyun reg = <0x1a>; 364*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 365*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 366*4882a593Smuzhiyun pinctrl-names = "default"; 367*4882a593Smuzhiyun pinctrl-0 = <&pmic_int_l>; 368*4882a593Smuzhiyun rockchip,system-power-controller; 369*4882a593Smuzhiyun wakeup-source; 370*4882a593Smuzhiyun gpio-controller; 371*4882a593Smuzhiyun #gpio-cells = <2>; 372*4882a593Smuzhiyun #clock-cells = <1>; 373*4882a593Smuzhiyun clock-output-names = "rk816-clkout1", "rk816-clkout2"; 374*4882a593Smuzhiyun extcon = <&u2phy>; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun vcc1-supply = <&vcc_sys>; 377*4882a593Smuzhiyun vcc2-supply = <&vcc_sys>; 378*4882a593Smuzhiyun vcc3-supply = <&vcc_sys>; 379*4882a593Smuzhiyun vcc4-supply = <&vcc_sys>; 380*4882a593Smuzhiyun vcc5-supply = <&vcc_io>; 381*4882a593Smuzhiyun vcc6-supply = <&vcc_sys>; 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun gpio { 384*4882a593Smuzhiyun status = "okay"; 385*4882a593Smuzhiyun }; 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun pwrkey { 388*4882a593Smuzhiyun status = "okay"; 389*4882a593Smuzhiyun }; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun rtc { 392*4882a593Smuzhiyun status = "okay"; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun battery { 396*4882a593Smuzhiyun compatible = "rk816-battery"; 397*4882a593Smuzhiyun ocv_table = < 3500 3625 3685 3697 3718 3735 3748 398*4882a593Smuzhiyun 3760 3774 3788 3802 3816 3834 3853 399*4882a593Smuzhiyun 3877 3908 3946 3975 4018 4071 4106>; 400*4882a593Smuzhiyun design_capacity = <2500>; 401*4882a593Smuzhiyun design_qmax = <2750>; 402*4882a593Smuzhiyun bat_res = <100>; 403*4882a593Smuzhiyun max_input_current = <1500>; 404*4882a593Smuzhiyun max_chrg_current = <1300>; 405*4882a593Smuzhiyun max_chrg_voltage = <4200>; 406*4882a593Smuzhiyun sleep_enter_current = <300>; 407*4882a593Smuzhiyun sleep_exit_current = <300>; 408*4882a593Smuzhiyun sleep_filter_current = <100>; 409*4882a593Smuzhiyun power_off_thresd = <3500>; 410*4882a593Smuzhiyun zero_algorithm_vol = <3850>; 411*4882a593Smuzhiyun max_soc_offset = <60>; 412*4882a593Smuzhiyun monitor_sec = <5>; 413*4882a593Smuzhiyun virtual_power = <0>; 414*4882a593Smuzhiyun power_dc2otg = <0>; 415*4882a593Smuzhiyun dc_det_adc = <0>; 416*4882a593Smuzhiyun }; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun regulators { 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun vdd_arm: DCDC_REG1{ 421*4882a593Smuzhiyun regulator-name= "vdd_arm"; 422*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 423*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 424*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 425*4882a593Smuzhiyun regulator-initial-mode = <1>; 426*4882a593Smuzhiyun regulator-always-on; 427*4882a593Smuzhiyun regulator-boot-on; 428*4882a593Smuzhiyun regulator-state-mem { 429*4882a593Smuzhiyun regulator-off-in-suspend; 430*4882a593Smuzhiyun regulator-suspend-microvolt = <900000>; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun }; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun vdd_log: DCDC_REG2 { 435*4882a593Smuzhiyun regulator-name= "vdd_logic"; 436*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 437*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 438*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 439*4882a593Smuzhiyun regulator-initial-mode = <1>; 440*4882a593Smuzhiyun regulator-always-on; 441*4882a593Smuzhiyun regulator-boot-on; 442*4882a593Smuzhiyun regulator-state-mem { 443*4882a593Smuzhiyun regulator-on-in-suspend; 444*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 445*4882a593Smuzhiyun }; 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 449*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 450*4882a593Smuzhiyun regulator-always-on; 451*4882a593Smuzhiyun regulator-boot-on; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun vcc_io: DCDC_REG4 { 455*4882a593Smuzhiyun regulator-name = "vcc_io"; 456*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 457*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 458*4882a593Smuzhiyun regulator-initial-mode = <1>; 459*4882a593Smuzhiyun regulator-always-on; 460*4882a593Smuzhiyun regulator-boot-on; 461*4882a593Smuzhiyun regulator-state-mem { 462*4882a593Smuzhiyun regulator-on-in-suspend; 463*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 464*4882a593Smuzhiyun }; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun vcc28_cif: LDO_REG1 { 468*4882a593Smuzhiyun regulator-name = "vcc28_cif"; 469*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 470*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 471*4882a593Smuzhiyun regulator-always-on; 472*4882a593Smuzhiyun regulator-boot-on; 473*4882a593Smuzhiyun regulator-state-mem { 474*4882a593Smuzhiyun regulator-off-in-suspend; 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun }; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun vcc18_cif: LDO_REG2 { 479*4882a593Smuzhiyun regulator-name = "vcc18_cif"; 480*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 481*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 482*4882a593Smuzhiyun regulator-always-on; 483*4882a593Smuzhiyun regulator-boot-on; 484*4882a593Smuzhiyun regulator-state-mem { 485*4882a593Smuzhiyun regulator-off-in-suspend; 486*4882a593Smuzhiyun }; 487*4882a593Smuzhiyun }; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun vdd_11: LDO_REG3 { 490*4882a593Smuzhiyun regulator-name = "vdd_11"; 491*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 492*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 493*4882a593Smuzhiyun regulator-always-on; 494*4882a593Smuzhiyun regulator-boot-on; 495*4882a593Smuzhiyun regulator-state-mem { 496*4882a593Smuzhiyun regulator-on-in-suspend; 497*4882a593Smuzhiyun regulator-suspend-microvolt = <1100000>; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun ldo4: LDO_REG4 { 502*4882a593Smuzhiyun regulator-name= "ldo4"; 503*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 504*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 505*4882a593Smuzhiyun regulator-always-on; 506*4882a593Smuzhiyun regulator-boot-on; 507*4882a593Smuzhiyun regulator-state-mem { 508*4882a593Smuzhiyun regulator-off-in-suspend; 509*4882a593Smuzhiyun }; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun ldo5: LDO_REG5 { 513*4882a593Smuzhiyun regulator-name= "ldo5"; 514*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 515*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 516*4882a593Smuzhiyun regulator-always-on; 517*4882a593Smuzhiyun regulator-boot-on; 518*4882a593Smuzhiyun regulator-state-mem { 519*4882a593Smuzhiyun regulator-on-in-suspend; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun }; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun ldo6: LDO_REG6 { 524*4882a593Smuzhiyun regulator-name= "ldo6"; 525*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 526*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 527*4882a593Smuzhiyun regulator-state-mem { 528*4882a593Smuzhiyun regulator-on-in-suspend; 529*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 530*4882a593Smuzhiyun }; 531*4882a593Smuzhiyun }; 532*4882a593Smuzhiyun }; 533*4882a593Smuzhiyun }; 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun sensor@4c { 536*4882a593Smuzhiyun compatible = "gs_mc3230"; 537*4882a593Smuzhiyun reg = <0x4c>; 538*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 539*4882a593Smuzhiyun irq_enable = <0>; 540*4882a593Smuzhiyun poll_delay_ms = <30>; 541*4882a593Smuzhiyun layout = <3>; 542*4882a593Smuzhiyun reprobe_en = <1>; 543*4882a593Smuzhiyun }; 544*4882a593Smuzhiyun}; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun&i2s_2ch { 547*4882a593Smuzhiyun #sound-dai-cells = <0>; 548*4882a593Smuzhiyun status = "okay"; 549*4882a593Smuzhiyun}; 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun&iep { 552*4882a593Smuzhiyun status = "okay"; 553*4882a593Smuzhiyun}; 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun&iep_mmu { 556*4882a593Smuzhiyun status = "okay"; 557*4882a593Smuzhiyun}; 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun&mpp_srv { 560*4882a593Smuzhiyun status = "okay"; 561*4882a593Smuzhiyun}; 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun&nandc { 564*4882a593Smuzhiyun status = "okay"; 565*4882a593Smuzhiyun}; 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun&pinctrl { 568*4882a593Smuzhiyun camera { 569*4882a593Smuzhiyun fcam_pd: fcam-pd { 570*4882a593Smuzhiyun rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 571*4882a593Smuzhiyun }; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun bcam_pd: bcam-pd { 574*4882a593Smuzhiyun rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 575*4882a593Smuzhiyun }; 576*4882a593Smuzhiyun }; 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun lcdc { 579*4882a593Smuzhiyun lcdc_lcdc: lcdc-lcdc { 580*4882a593Smuzhiyun rockchip,pins = 581*4882a593Smuzhiyun /* depend on the hardware */ 582*4882a593Smuzhiyun <2 RK_PB0 1 &pcfg_pull_none>, /* DCLK */ 583*4882a593Smuzhiyun /* <2 RK_PB1 1 &pcfg_pull_none>, *//* HSYNC */ 584*4882a593Smuzhiyun /* <2 RK_PB2 1 &pcfg_pull_none>, *//* VSYNC */ 585*4882a593Smuzhiyun <2 RK_PB3 1 &pcfg_pull_none>, /* DEN */ 586*4882a593Smuzhiyun <2 RK_PB4 1 &pcfg_pull_none>, /* DATA10 */ 587*4882a593Smuzhiyun <2 RK_PB5 1 &pcfg_pull_none>, /* DATA11 */ 588*4882a593Smuzhiyun <2 RK_PB6 1 &pcfg_pull_none>, /* DATA12 */ 589*4882a593Smuzhiyun <2 RK_PB7 1 &pcfg_pull_none>, /* DATA13 */ 590*4882a593Smuzhiyun <2 RK_PC0 1 &pcfg_pull_none>, /* DATA14 */ 591*4882a593Smuzhiyun <2 RK_PC1 1 &pcfg_pull_none>, /* DATA15 */ 592*4882a593Smuzhiyun <2 RK_PC2 1 &pcfg_pull_none>, /* DATA16 */ 593*4882a593Smuzhiyun <2 RK_PC3 1 &pcfg_pull_none>; /* DATA17 */ 594*4882a593Smuzhiyun /* <2 RK_PC4 1 &pcfg_pull_none>, *//* DATA18 */ 595*4882a593Smuzhiyun /* <2 RK_PC5 1 &pcfg_pull_none>, *//* DATA19 */ 596*4882a593Smuzhiyun /* <2 RK_PC6 1 &pcfg_pull_none>, *//* DATA20 */ 597*4882a593Smuzhiyun /* <2 RK_PC7 1 &pcfg_pull_none>, *//* DATA21 */ 598*4882a593Smuzhiyun /* <2 RK_PD0 1 &pcfg_pull_none>, *//* DATA22 */ 599*4882a593Smuzhiyun /* <2 RK_PD1 1 &pcfg_pull_none>; *//* DATA23 */ 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun }; 602*4882a593Smuzhiyun 603*4882a593Smuzhiyun pmic { 604*4882a593Smuzhiyun pmic_int_l: pmic-int-l { 605*4882a593Smuzhiyun rockchip,pins = 606*4882a593Smuzhiyun <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>; 607*4882a593Smuzhiyun }; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun uart1 { 611*4882a593Smuzhiyun uart1_xfer: uart1-xfer { 612*4882a593Smuzhiyun rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, 613*4882a593Smuzhiyun <1 RK_PB2 2 &pcfg_pull_default>; 614*4882a593Smuzhiyun }; 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun wireless-bluetooth { 618*4882a593Smuzhiyun uart1_rts_gpio: uart1-rts-gpio { 619*4882a593Smuzhiyun rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 620*4882a593Smuzhiyun }; 621*4882a593Smuzhiyun }; 622*4882a593Smuzhiyun}; 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun&pwm0 { 625*4882a593Smuzhiyun status = "okay"; 626*4882a593Smuzhiyun}; 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun&rga { 629*4882a593Smuzhiyun status = "okay"; 630*4882a593Smuzhiyun}; 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun&saradc { 633*4882a593Smuzhiyun status = "okay"; 634*4882a593Smuzhiyun vref-supply = <&vccadc_ref>; 635*4882a593Smuzhiyun}; 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun&sdmmc { 638*4882a593Smuzhiyun cap-mmc-highspeed; 639*4882a593Smuzhiyun no-sdio; 640*4882a593Smuzhiyun no-mmc; 641*4882a593Smuzhiyun card-detect-delay = <800>; 642*4882a593Smuzhiyun ignore-pm-notify; 643*4882a593Smuzhiyun keep-power-in-suspend; 644*4882a593Smuzhiyun cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; /* CD GPIO */ 645*4882a593Smuzhiyun status = "disabled"; 646*4882a593Smuzhiyun}; 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun&sdio { 649*4882a593Smuzhiyun max-frequency = <50000000>; 650*4882a593Smuzhiyun cap-sd-highspeed; 651*4882a593Smuzhiyun no-sd; 652*4882a593Smuzhiyun no-mmc; 653*4882a593Smuzhiyun ignore-pm-notify; 654*4882a593Smuzhiyun keep-power-in-suspend; 655*4882a593Smuzhiyun non-removable; 656*4882a593Smuzhiyun vmmc-supply = <&ldo5>; 657*4882a593Smuzhiyun status = "okay"; 658*4882a593Smuzhiyun}; 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun&tsadc { 661*4882a593Smuzhiyun status = "okay"; 662*4882a593Smuzhiyun}; 663*4882a593Smuzhiyun 664*4882a593Smuzhiyun&u2phy { 665*4882a593Smuzhiyun status = "okay"; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun u2phy_otg: otg-port { 668*4882a593Smuzhiyun status = "okay"; 669*4882a593Smuzhiyun }; 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun u2phy_host: host-port { 672*4882a593Smuzhiyun status = "okay"; 673*4882a593Smuzhiyun }; 674*4882a593Smuzhiyun}; 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun&uart1 { 677*4882a593Smuzhiyun pinctrl-names = "default"; 678*4882a593Smuzhiyun pinctrl-0 = <&uart1_xfer &uart1_cts>; 679*4882a593Smuzhiyun status = "okay"; 680*4882a593Smuzhiyun}; 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun&usb_otg { 683*4882a593Smuzhiyun status = "okay"; 684*4882a593Smuzhiyun}; 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun&vop { 687*4882a593Smuzhiyun status = "okay"; 688*4882a593Smuzhiyun}; 689*4882a593Smuzhiyun 690*4882a593Smuzhiyun&vop_mmu { 691*4882a593Smuzhiyun status = "okay"; 692*4882a593Smuzhiyun}; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun&vdpu { 695*4882a593Smuzhiyun status = "okay"; 696*4882a593Smuzhiyun}; 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun&vepu { 699*4882a593Smuzhiyun status = "okay"; 700*4882a593Smuzhiyun}; 701*4882a593Smuzhiyun 702*4882a593Smuzhiyun&vpu_mmu { 703*4882a593Smuzhiyun status = "okay"; 704*4882a593Smuzhiyun}; 705