xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/r8a7794-alt.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the Alt board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Renesas Electronics Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/dts-v1/;
9*4882a593Smuzhiyun#include "r8a7794.dtsi"
10*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Alt";
14*4882a593Smuzhiyun	compatible = "renesas,alt", "renesas,r8a7794";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	aliases {
17*4882a593Smuzhiyun		serial0 = &scif2;
18*4882a593Smuzhiyun		i2c9 = &gpioi2c1;
19*4882a593Smuzhiyun		i2c10 = &gpioi2c4;
20*4882a593Smuzhiyun		i2c11 = &i2chdmi;
21*4882a593Smuzhiyun		i2c12 = &i2cexio4;
22*4882a593Smuzhiyun		mmc0 = &mmcif0;
23*4882a593Smuzhiyun		mmc1 = &sdhi0;
24*4882a593Smuzhiyun		mmc2 = &sdhi1;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	chosen {
28*4882a593Smuzhiyun		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
29*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	memory@40000000 {
33*4882a593Smuzhiyun		device_type = "memory";
34*4882a593Smuzhiyun		reg = <0 0x40000000 0 0x40000000>;
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	d3_3v: regulator-d3-3v {
38*4882a593Smuzhiyun		compatible = "regulator-fixed";
39*4882a593Smuzhiyun		regulator-name = "D3.3V";
40*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
41*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
42*4882a593Smuzhiyun		regulator-boot-on;
43*4882a593Smuzhiyun		regulator-always-on;
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	vcc_sdhi0: regulator-vcc-sdhi0 {
47*4882a593Smuzhiyun		compatible = "regulator-fixed";
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun		regulator-name = "SDHI0 Vcc";
50*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
51*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun		gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
54*4882a593Smuzhiyun		enable-active-high;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	vccq_sdhi0: regulator-vccq-sdhi0 {
58*4882a593Smuzhiyun		compatible = "regulator-gpio";
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		regulator-name = "SDHI0 VccQ";
61*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
62*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun		gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
65*4882a593Smuzhiyun		gpios-states = <1>;
66*4882a593Smuzhiyun		states = <3300000 1>, <1800000 0>;
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	vcc_sdhi1: regulator-vcc-sdhi1 {
70*4882a593Smuzhiyun		compatible = "regulator-fixed";
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun		regulator-name = "SDHI1 Vcc";
73*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
74*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun		gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
77*4882a593Smuzhiyun		enable-active-high;
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	vccq_sdhi1: regulator-vccq-sdhi1 {
81*4882a593Smuzhiyun		compatible = "regulator-gpio";
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun		regulator-name = "SDHI1 VccQ";
84*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
85*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
88*4882a593Smuzhiyun		gpios-states = <1>;
89*4882a593Smuzhiyun		states = <3300000 1>, <1800000 0>;
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun	lbsc {
93*4882a593Smuzhiyun		#address-cells = <1>;
94*4882a593Smuzhiyun		#size-cells = <1>;
95*4882a593Smuzhiyun	};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun	vga-encoder {
98*4882a593Smuzhiyun		compatible = "adi,adv7123";
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun		ports {
101*4882a593Smuzhiyun			#address-cells = <1>;
102*4882a593Smuzhiyun			#size-cells = <0>;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun			port@0 {
105*4882a593Smuzhiyun				reg = <0>;
106*4882a593Smuzhiyun				adv7123_in: endpoint {
107*4882a593Smuzhiyun					remote-endpoint = <&du_out_rgb1>;
108*4882a593Smuzhiyun				};
109*4882a593Smuzhiyun			};
110*4882a593Smuzhiyun			port@1 {
111*4882a593Smuzhiyun				reg = <1>;
112*4882a593Smuzhiyun				adv7123_out: endpoint {
113*4882a593Smuzhiyun					remote-endpoint = <&vga_in>;
114*4882a593Smuzhiyun				};
115*4882a593Smuzhiyun			};
116*4882a593Smuzhiyun		};
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun	vga {
120*4882a593Smuzhiyun		compatible = "vga-connector";
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun		port {
123*4882a593Smuzhiyun			vga_in: endpoint {
124*4882a593Smuzhiyun				remote-endpoint = <&adv7123_out>;
125*4882a593Smuzhiyun			};
126*4882a593Smuzhiyun		};
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun	x2_clk: x2-clock {
130*4882a593Smuzhiyun		compatible = "fixed-clock";
131*4882a593Smuzhiyun		#clock-cells = <0>;
132*4882a593Smuzhiyun		clock-frequency = <74250000>;
133*4882a593Smuzhiyun	};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun	x13_clk: x13-clock {
136*4882a593Smuzhiyun		compatible = "fixed-clock";
137*4882a593Smuzhiyun		#clock-cells = <0>;
138*4882a593Smuzhiyun		clock-frequency = <148500000>;
139*4882a593Smuzhiyun	};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun	gpioi2c1: i2c-9 {
142*4882a593Smuzhiyun		#address-cells = <1>;
143*4882a593Smuzhiyun		#size-cells = <0>;
144*4882a593Smuzhiyun		compatible = "i2c-gpio";
145*4882a593Smuzhiyun		status = "disabled";
146*4882a593Smuzhiyun		scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
147*4882a593Smuzhiyun		sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	gpioi2c4: i2c-10 {
151*4882a593Smuzhiyun		#address-cells = <1>;
152*4882a593Smuzhiyun		#size-cells = <0>;
153*4882a593Smuzhiyun		compatible = "i2c-gpio";
154*4882a593Smuzhiyun		status = "disabled";
155*4882a593Smuzhiyun		scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
156*4882a593Smuzhiyun		sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
157*4882a593Smuzhiyun		i2c-gpio,delay-us = <5>;
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	/*
161*4882a593Smuzhiyun	 * A fallback to GPIO is provided for I2C1.
162*4882a593Smuzhiyun	 */
163*4882a593Smuzhiyun	i2chdmi: i2c-11 {
164*4882a593Smuzhiyun		compatible = "i2c-demux-pinctrl";
165*4882a593Smuzhiyun		i2c-parent = <&i2c1>, <&gpioi2c1>;
166*4882a593Smuzhiyun		i2c-bus-name = "i2c-hdmi";
167*4882a593Smuzhiyun		#address-cells = <1>;
168*4882a593Smuzhiyun		#size-cells = <0>;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun		composite-in@20 {
171*4882a593Smuzhiyun			compatible = "adi,adv7180";
172*4882a593Smuzhiyun			reg = <0x20>;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun			port {
175*4882a593Smuzhiyun				adv7180: endpoint {
176*4882a593Smuzhiyun					bus-width = <8>;
177*4882a593Smuzhiyun					remote-endpoint = <&vin0ep>;
178*4882a593Smuzhiyun				};
179*4882a593Smuzhiyun			};
180*4882a593Smuzhiyun		};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun		eeprom@50 {
183*4882a593Smuzhiyun			compatible = "renesas,r1ex24002", "atmel,24c02";
184*4882a593Smuzhiyun			reg = <0x50>;
185*4882a593Smuzhiyun			pagesize = <16>;
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	/*
190*4882a593Smuzhiyun	 * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
191*4882a593Smuzhiyun	 * A fallback to GPIO is provided.
192*4882a593Smuzhiyun	 */
193*4882a593Smuzhiyun	i2cexio4: i2c-14 {
194*4882a593Smuzhiyun		compatible = "i2c-demux-pinctrl";
195*4882a593Smuzhiyun		i2c-parent = <&i2c4>, <&gpioi2c4>;
196*4882a593Smuzhiyun		i2c-bus-name = "i2c-exio4";
197*4882a593Smuzhiyun		#address-cells = <1>;
198*4882a593Smuzhiyun		#size-cells = <0>;
199*4882a593Smuzhiyun	};
200*4882a593Smuzhiyun};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun&pci0 {
203*4882a593Smuzhiyun	status = "okay";
204*4882a593Smuzhiyun	pinctrl-0 = <&usb0_pins>;
205*4882a593Smuzhiyun	pinctrl-names = "default";
206*4882a593Smuzhiyun};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun&pci1 {
209*4882a593Smuzhiyun	status = "okay";
210*4882a593Smuzhiyun	pinctrl-0 = <&usb1_pins>;
211*4882a593Smuzhiyun	pinctrl-names = "default";
212*4882a593Smuzhiyun};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun&usbphy {
215*4882a593Smuzhiyun	status = "okay";
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun&du {
219*4882a593Smuzhiyun	pinctrl-0 = <&du_pins>;
220*4882a593Smuzhiyun	pinctrl-names = "default";
221*4882a593Smuzhiyun	status = "okay";
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
224*4882a593Smuzhiyun		 <&x13_clk>, <&x2_clk>;
225*4882a593Smuzhiyun	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun	ports {
228*4882a593Smuzhiyun		port@1 {
229*4882a593Smuzhiyun			endpoint {
230*4882a593Smuzhiyun				remote-endpoint = <&adv7123_in>;
231*4882a593Smuzhiyun			};
232*4882a593Smuzhiyun		};
233*4882a593Smuzhiyun	};
234*4882a593Smuzhiyun};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun&extal_clk {
237*4882a593Smuzhiyun	clock-frequency = <20000000>;
238*4882a593Smuzhiyun};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun&pfc {
241*4882a593Smuzhiyun	pinctrl-0 = <&scif_clk_pins>;
242*4882a593Smuzhiyun	pinctrl-names = "default";
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun	du_pins: du {
245*4882a593Smuzhiyun		groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
246*4882a593Smuzhiyun		function = "du1";
247*4882a593Smuzhiyun	};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun	scif2_pins: scif2 {
250*4882a593Smuzhiyun		groups = "scif2_data";
251*4882a593Smuzhiyun		function = "scif2";
252*4882a593Smuzhiyun	};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun	scif_clk_pins: scif_clk {
255*4882a593Smuzhiyun		groups = "scif_clk";
256*4882a593Smuzhiyun		function = "scif_clk";
257*4882a593Smuzhiyun	};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun	ether_pins: ether {
260*4882a593Smuzhiyun		groups = "eth_link", "eth_mdio", "eth_rmii";
261*4882a593Smuzhiyun		function = "eth";
262*4882a593Smuzhiyun	};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun	phy1_pins: phy1 {
265*4882a593Smuzhiyun		groups = "intc_irq8";
266*4882a593Smuzhiyun		function = "intc";
267*4882a593Smuzhiyun	};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun	i2c1_pins: i2c1 {
270*4882a593Smuzhiyun		groups = "i2c1";
271*4882a593Smuzhiyun		function = "i2c1";
272*4882a593Smuzhiyun	};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun	i2c4_pins: i2c4 {
275*4882a593Smuzhiyun		groups = "i2c4";
276*4882a593Smuzhiyun		function = "i2c4";
277*4882a593Smuzhiyun	};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun	vin0_pins: vin0 {
280*4882a593Smuzhiyun		groups = "vin0_data8", "vin0_clk";
281*4882a593Smuzhiyun		function = "vin0";
282*4882a593Smuzhiyun	};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun	mmcif0_pins: mmcif0 {
285*4882a593Smuzhiyun		groups = "mmc_data8", "mmc_ctrl";
286*4882a593Smuzhiyun		function = "mmc";
287*4882a593Smuzhiyun	};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun	sdhi0_pins: sd0 {
290*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
291*4882a593Smuzhiyun		function = "sdhi0";
292*4882a593Smuzhiyun		power-source = <3300>;
293*4882a593Smuzhiyun	};
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun	sdhi0_pins_uhs: sd0_uhs {
296*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
297*4882a593Smuzhiyun		function = "sdhi0";
298*4882a593Smuzhiyun		power-source = <1800>;
299*4882a593Smuzhiyun	};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun	sdhi1_pins: sd1 {
302*4882a593Smuzhiyun		groups = "sdhi1_data4", "sdhi1_ctrl";
303*4882a593Smuzhiyun		function = "sdhi1";
304*4882a593Smuzhiyun		power-source = <3300>;
305*4882a593Smuzhiyun	};
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun	sdhi1_pins_uhs: sd1_uhs {
308*4882a593Smuzhiyun		groups = "sdhi1_data4", "sdhi1_ctrl";
309*4882a593Smuzhiyun		function = "sdhi1";
310*4882a593Smuzhiyun		power-source = <1800>;
311*4882a593Smuzhiyun	};
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun	usb0_pins: usb0 {
314*4882a593Smuzhiyun		groups = "usb0";
315*4882a593Smuzhiyun		function = "usb0";
316*4882a593Smuzhiyun	};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun	usb1_pins: usb1 {
319*4882a593Smuzhiyun		groups = "usb1";
320*4882a593Smuzhiyun		function = "usb1";
321*4882a593Smuzhiyun	};
322*4882a593Smuzhiyun};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun&cmt0 {
325*4882a593Smuzhiyun	status = "okay";
326*4882a593Smuzhiyun};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun&pfc {
329*4882a593Smuzhiyun	qspi_pins: qspi {
330*4882a593Smuzhiyun		groups = "qspi_ctrl", "qspi_data4";
331*4882a593Smuzhiyun		function = "qspi";
332*4882a593Smuzhiyun	};
333*4882a593Smuzhiyun};
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun&ether {
336*4882a593Smuzhiyun	pinctrl-0 = <&ether_pins &phy1_pins>;
337*4882a593Smuzhiyun	pinctrl-names = "default";
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun	phy-handle = <&phy1>;
340*4882a593Smuzhiyun	renesas,ether-link-active-low;
341*4882a593Smuzhiyun	status = "okay";
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun	phy1: ethernet-phy@1 {
344*4882a593Smuzhiyun		reg = <1>;
345*4882a593Smuzhiyun		interrupt-parent = <&irqc0>;
346*4882a593Smuzhiyun		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
347*4882a593Smuzhiyun		micrel,led-mode = <1>;
348*4882a593Smuzhiyun		reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
349*4882a593Smuzhiyun	};
350*4882a593Smuzhiyun};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun&mmcif0 {
353*4882a593Smuzhiyun	pinctrl-0 = <&mmcif0_pins>;
354*4882a593Smuzhiyun	pinctrl-names = "default";
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun	vmmc-supply = <&d3_3v>;
357*4882a593Smuzhiyun	vqmmc-supply = <&d3_3v>;
358*4882a593Smuzhiyun	bus-width = <8>;
359*4882a593Smuzhiyun	non-removable;
360*4882a593Smuzhiyun	status = "okay";
361*4882a593Smuzhiyun};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun&rwdt {
364*4882a593Smuzhiyun	timeout-sec = <60>;
365*4882a593Smuzhiyun	status = "okay";
366*4882a593Smuzhiyun};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun&sdhi0 {
369*4882a593Smuzhiyun	pinctrl-0 = <&sdhi0_pins>;
370*4882a593Smuzhiyun	pinctrl-1 = <&sdhi0_pins_uhs>;
371*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi0>;
374*4882a593Smuzhiyun	vqmmc-supply = <&vccq_sdhi0>;
375*4882a593Smuzhiyun	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
376*4882a593Smuzhiyun	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
377*4882a593Smuzhiyun	sd-uhs-sdr50;
378*4882a593Smuzhiyun	sd-uhs-sdr104;
379*4882a593Smuzhiyun	status = "okay";
380*4882a593Smuzhiyun};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun&sdhi1 {
383*4882a593Smuzhiyun	pinctrl-0 = <&sdhi1_pins>;
384*4882a593Smuzhiyun	pinctrl-1 = <&sdhi1_pins_uhs>;
385*4882a593Smuzhiyun	pinctrl-names = "default", "state_uhs";
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi1>;
388*4882a593Smuzhiyun	vqmmc-supply = <&vccq_sdhi1>;
389*4882a593Smuzhiyun	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
390*4882a593Smuzhiyun	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
391*4882a593Smuzhiyun	sd-uhs-sdr50;
392*4882a593Smuzhiyun	status = "okay";
393*4882a593Smuzhiyun};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun&i2c1 {
396*4882a593Smuzhiyun	pinctrl-0 = <&i2c1_pins>;
397*4882a593Smuzhiyun	pinctrl-names = "i2c-hdmi";
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun	clock-frequency = <400000>;
400*4882a593Smuzhiyun};
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun&i2c4 {
403*4882a593Smuzhiyun	pinctrl-0 = <&i2c4_pins>;
404*4882a593Smuzhiyun	pinctrl-names = "i2c-exio4";
405*4882a593Smuzhiyun};
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun&i2c7 {
408*4882a593Smuzhiyun	status = "okay";
409*4882a593Smuzhiyun	clock-frequency = <100000>;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun	pmic@58 {
412*4882a593Smuzhiyun		compatible = "dlg,da9063";
413*4882a593Smuzhiyun		reg = <0x58>;
414*4882a593Smuzhiyun		interrupt-parent = <&gpio3>;
415*4882a593Smuzhiyun		interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
416*4882a593Smuzhiyun		interrupt-controller;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun		rtc {
419*4882a593Smuzhiyun			compatible = "dlg,da9063-rtc";
420*4882a593Smuzhiyun		};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun		wdt {
423*4882a593Smuzhiyun			compatible = "dlg,da9063-watchdog";
424*4882a593Smuzhiyun		};
425*4882a593Smuzhiyun	};
426*4882a593Smuzhiyun};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun&vin0 {
429*4882a593Smuzhiyun	status = "okay";
430*4882a593Smuzhiyun	pinctrl-0 = <&vin0_pins>;
431*4882a593Smuzhiyun	pinctrl-names = "default";
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun	port {
434*4882a593Smuzhiyun		vin0ep: endpoint {
435*4882a593Smuzhiyun			remote-endpoint = <&adv7180>;
436*4882a593Smuzhiyun			bus-width = <8>;
437*4882a593Smuzhiyun		};
438*4882a593Smuzhiyun	};
439*4882a593Smuzhiyun};
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun&scif2 {
442*4882a593Smuzhiyun	pinctrl-0 = <&scif2_pins>;
443*4882a593Smuzhiyun	pinctrl-names = "default";
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun	status = "okay";
446*4882a593Smuzhiyun};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun&scif_clk {
449*4882a593Smuzhiyun	clock-frequency = <14745600>;
450*4882a593Smuzhiyun};
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun&qspi {
453*4882a593Smuzhiyun	pinctrl-0 = <&qspi_pins>;
454*4882a593Smuzhiyun	pinctrl-names = "default";
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun	status = "okay";
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun	flash@0 {
459*4882a593Smuzhiyun		compatible = "spansion,s25fl512s", "jedec,spi-nor";
460*4882a593Smuzhiyun		reg = <0>;
461*4882a593Smuzhiyun		spi-max-frequency = <30000000>;
462*4882a593Smuzhiyun		spi-tx-bus-width = <4>;
463*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
464*4882a593Smuzhiyun		spi-cpol;
465*4882a593Smuzhiyun		spi-cpha;
466*4882a593Smuzhiyun		m25p,fast-read;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun		partitions {
469*4882a593Smuzhiyun			compatible = "fixed-partitions";
470*4882a593Smuzhiyun			#address-cells = <1>;
471*4882a593Smuzhiyun			#size-cells = <1>;
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun			partition@0 {
474*4882a593Smuzhiyun				label = "loader";
475*4882a593Smuzhiyun				reg = <0x00000000 0x00040000>;
476*4882a593Smuzhiyun				read-only;
477*4882a593Smuzhiyun			};
478*4882a593Smuzhiyun			partition@40000 {
479*4882a593Smuzhiyun				label = "system";
480*4882a593Smuzhiyun				reg = <0x00040000 0x00040000>;
481*4882a593Smuzhiyun				read-only;
482*4882a593Smuzhiyun			};
483*4882a593Smuzhiyun			partition@80000 {
484*4882a593Smuzhiyun				label = "user";
485*4882a593Smuzhiyun				reg = <0x00080000 0x03f80000>;
486*4882a593Smuzhiyun			};
487*4882a593Smuzhiyun		};
488*4882a593Smuzhiyun	};
489*4882a593Smuzhiyun};
490