xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/r8a7792-blanche.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the Blanche board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Renesas Electronics Corporation
6*4882a593Smuzhiyun * Copyright (C) 2016 Cogent  Embedded, Inc.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/dts-v1/;
10*4882a593Smuzhiyun#include "r8a7792.dtsi"
11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
12*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	model = "Blanche";
16*4882a593Smuzhiyun	compatible = "renesas,blanche", "renesas,r8a7792";
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	aliases {
19*4882a593Smuzhiyun		serial0 = &scif0;
20*4882a593Smuzhiyun		serial1 = &scif3;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	chosen {
24*4882a593Smuzhiyun		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
25*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	memory@40000000 {
29*4882a593Smuzhiyun		device_type = "memory";
30*4882a593Smuzhiyun		reg = <0 0x40000000 0 0x40000000>;
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	d3_3v: regulator-3v3 {
34*4882a593Smuzhiyun		compatible = "regulator-fixed";
35*4882a593Smuzhiyun		regulator-name = "D3.3V";
36*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
37*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
38*4882a593Smuzhiyun		regulator-boot-on;
39*4882a593Smuzhiyun		regulator-always-on;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	ethernet@18000000 {
43*4882a593Smuzhiyun		compatible = "smsc,lan89218", "smsc,lan9115";
44*4882a593Smuzhiyun		reg = <0 0x18000000 0 0x100>;
45*4882a593Smuzhiyun		phy-mode = "mii";
46*4882a593Smuzhiyun		interrupt-parent = <&irqc>;
47*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
48*4882a593Smuzhiyun		smsc,irq-push-pull;
49*4882a593Smuzhiyun		reg-io-width = <4>;
50*4882a593Smuzhiyun		vddvario-supply = <&d3_3v>;
51*4882a593Smuzhiyun		vdd33a-supply = <&d3_3v>;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun		pinctrl-0 = <&lan89218_pins>;
54*4882a593Smuzhiyun		pinctrl-names = "default";
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	vga-encoder {
58*4882a593Smuzhiyun		compatible = "adi,adv7123";
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		ports {
61*4882a593Smuzhiyun			#address-cells = <1>;
62*4882a593Smuzhiyun			#size-cells = <0>;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun			port@0 {
65*4882a593Smuzhiyun				reg = <0>;
66*4882a593Smuzhiyun				adv7123_in: endpoint {
67*4882a593Smuzhiyun					remote-endpoint = <&du_out_rgb1>;
68*4882a593Smuzhiyun				};
69*4882a593Smuzhiyun			};
70*4882a593Smuzhiyun			port@1 {
71*4882a593Smuzhiyun				reg = <1>;
72*4882a593Smuzhiyun				adv7123_out: endpoint {
73*4882a593Smuzhiyun					remote-endpoint = <&vga_in>;
74*4882a593Smuzhiyun				};
75*4882a593Smuzhiyun			};
76*4882a593Smuzhiyun		};
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	hdmi-out {
80*4882a593Smuzhiyun		compatible = "hdmi-connector";
81*4882a593Smuzhiyun		type = "a";
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun		port {
84*4882a593Smuzhiyun			hdmi_con: endpoint {
85*4882a593Smuzhiyun				remote-endpoint = <&adv7511_out>;
86*4882a593Smuzhiyun			};
87*4882a593Smuzhiyun		};
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	vga {
91*4882a593Smuzhiyun		compatible = "vga-connector";
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		port {
94*4882a593Smuzhiyun			vga_in: endpoint {
95*4882a593Smuzhiyun				remote-endpoint = <&adv7123_out>;
96*4882a593Smuzhiyun			};
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	x1_clk: x1 {
101*4882a593Smuzhiyun		compatible = "fixed-clock";
102*4882a593Smuzhiyun		#clock-cells = <0>;
103*4882a593Smuzhiyun		clock-frequency = <74250000>;
104*4882a593Smuzhiyun	};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun	x2_clk: x2 {
107*4882a593Smuzhiyun		compatible = "fixed-clock";
108*4882a593Smuzhiyun		#clock-cells = <0>;
109*4882a593Smuzhiyun		clock-frequency = <65000000>;
110*4882a593Smuzhiyun	};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun	keyboard {
113*4882a593Smuzhiyun		compatible = "gpio-keys";
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun		key-1 {
116*4882a593Smuzhiyun			linux,code = <KEY_1>;
117*4882a593Smuzhiyun			label = "SW2-1";
118*4882a593Smuzhiyun			wakeup-source;
119*4882a593Smuzhiyun			debounce-interval = <20>;
120*4882a593Smuzhiyun			gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
121*4882a593Smuzhiyun		};
122*4882a593Smuzhiyun		key-2 {
123*4882a593Smuzhiyun			linux,code = <KEY_2>;
124*4882a593Smuzhiyun			label = "SW2-2";
125*4882a593Smuzhiyun			wakeup-source;
126*4882a593Smuzhiyun			debounce-interval = <20>;
127*4882a593Smuzhiyun			gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
128*4882a593Smuzhiyun		};
129*4882a593Smuzhiyun		key-3 {
130*4882a593Smuzhiyun			linux,code = <KEY_3>;
131*4882a593Smuzhiyun			label = "SW2-3";
132*4882a593Smuzhiyun			wakeup-source;
133*4882a593Smuzhiyun			debounce-interval = <20>;
134*4882a593Smuzhiyun			gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
135*4882a593Smuzhiyun		};
136*4882a593Smuzhiyun		key-4 {
137*4882a593Smuzhiyun			linux,code = <KEY_4>;
138*4882a593Smuzhiyun			label = "SW2-4";
139*4882a593Smuzhiyun			wakeup-source;
140*4882a593Smuzhiyun			debounce-interval = <20>;
141*4882a593Smuzhiyun			gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
142*4882a593Smuzhiyun		};
143*4882a593Smuzhiyun		key-a {
144*4882a593Smuzhiyun			linux,code = <KEY_A>;
145*4882a593Smuzhiyun			label = "SW24";
146*4882a593Smuzhiyun			wakeup-source;
147*4882a593Smuzhiyun			debounce-interval = <20>;
148*4882a593Smuzhiyun			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
149*4882a593Smuzhiyun		};
150*4882a593Smuzhiyun		key-b {
151*4882a593Smuzhiyun			linux,code = <KEY_B>;
152*4882a593Smuzhiyun			label = "SW25";
153*4882a593Smuzhiyun			wakeup-source;
154*4882a593Smuzhiyun			debounce-interval = <20>;
155*4882a593Smuzhiyun			gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
156*4882a593Smuzhiyun		};
157*4882a593Smuzhiyun	};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun	leds {
160*4882a593Smuzhiyun		compatible = "gpio-leds";
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun		led17 {
163*4882a593Smuzhiyun			gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>;
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun		led18 {
166*4882a593Smuzhiyun			gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>;
167*4882a593Smuzhiyun		};
168*4882a593Smuzhiyun		led19 {
169*4882a593Smuzhiyun			gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>;
170*4882a593Smuzhiyun		};
171*4882a593Smuzhiyun		led20 {
172*4882a593Smuzhiyun			gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>;
173*4882a593Smuzhiyun		};
174*4882a593Smuzhiyun	};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun	vcc_sdhi0: regulator-vcc-sdhi0 {
177*4882a593Smuzhiyun		compatible = "regulator-fixed";
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun		regulator-name = "SDHI0 Vcc";
180*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
181*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun		gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
184*4882a593Smuzhiyun		enable-active-high;
185*4882a593Smuzhiyun	};
186*4882a593Smuzhiyun};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&extal_clk {
189*4882a593Smuzhiyun	clock-frequency = <20000000>;
190*4882a593Smuzhiyun};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun&can_clk {
193*4882a593Smuzhiyun	clock-frequency = <48000000>;
194*4882a593Smuzhiyun};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun&pfc {
197*4882a593Smuzhiyun	scif0_pins: scif0 {
198*4882a593Smuzhiyun		groups = "scif0_data";
199*4882a593Smuzhiyun		function = "scif0";
200*4882a593Smuzhiyun	};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun	scif3_pins: scif3 {
203*4882a593Smuzhiyun		groups = "scif3_data";
204*4882a593Smuzhiyun		function = "scif3";
205*4882a593Smuzhiyun	};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun	lan89218_pins: lan89218 {
208*4882a593Smuzhiyun		intc {
209*4882a593Smuzhiyun			groups = "intc_irq0";
210*4882a593Smuzhiyun			function = "intc";
211*4882a593Smuzhiyun		};
212*4882a593Smuzhiyun		lbsc {
213*4882a593Smuzhiyun			groups = "lbsc_ex_cs0";
214*4882a593Smuzhiyun			function = "lbsc";
215*4882a593Smuzhiyun		};
216*4882a593Smuzhiyun	};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun	can0_pins: can0 {
219*4882a593Smuzhiyun		groups = "can0_data", "can_clk";
220*4882a593Smuzhiyun		function = "can0";
221*4882a593Smuzhiyun	};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	sdhi0_pins: sdhi0 {
224*4882a593Smuzhiyun		groups = "sdhi0_data4", "sdhi0_ctrl";
225*4882a593Smuzhiyun		function = "sdhi0";
226*4882a593Smuzhiyun	};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun	du0_pins: du0 {
229*4882a593Smuzhiyun		groups = "du0_rgb888", "du0_sync", "du0_disp";
230*4882a593Smuzhiyun		function = "du0";
231*4882a593Smuzhiyun	};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun	du1_pins: du1 {
234*4882a593Smuzhiyun		groups = "du1_rgb666", "du1_sync", "du1_disp";
235*4882a593Smuzhiyun		function = "du1";
236*4882a593Smuzhiyun	};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun	pmic_irq_pins: pmicirq {
239*4882a593Smuzhiyun		groups = "intc_irq2";
240*4882a593Smuzhiyun		function = "intc";
241*4882a593Smuzhiyun	};
242*4882a593Smuzhiyun};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun&rwdt {
245*4882a593Smuzhiyun	timeout-sec = <60>;
246*4882a593Smuzhiyun	status = "okay";
247*4882a593Smuzhiyun};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun&scif0 {
250*4882a593Smuzhiyun	pinctrl-0 = <&scif0_pins>;
251*4882a593Smuzhiyun	pinctrl-names = "default";
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun	status = "okay";
254*4882a593Smuzhiyun};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun&scif3 {
257*4882a593Smuzhiyun	pinctrl-0 = <&scif3_pins>;
258*4882a593Smuzhiyun	pinctrl-names = "default";
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun	status = "okay";
261*4882a593Smuzhiyun};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun&can0 {
264*4882a593Smuzhiyun	pinctrl-0 = <&can0_pins>;
265*4882a593Smuzhiyun	pinctrl-names = "default";
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun	status = "okay";
268*4882a593Smuzhiyun};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun&sdhi0 {
271*4882a593Smuzhiyun	pinctrl-0 = <&sdhi0_pins>;
272*4882a593Smuzhiyun	pinctrl-names = "default";
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun	vmmc-supply = <&vcc_sdhi0>;
275*4882a593Smuzhiyun	cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
276*4882a593Smuzhiyun	status = "okay";
277*4882a593Smuzhiyun};
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun&i2c1 {
280*4882a593Smuzhiyun	status = "okay";
281*4882a593Smuzhiyun	clock-frequency = <400000>;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun	hdmi@39 {
284*4882a593Smuzhiyun		compatible = "adi,adv7511w";
285*4882a593Smuzhiyun		reg = <0x39>;
286*4882a593Smuzhiyun		interrupt-parent = <&irqc>;
287*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun		adi,input-depth = <8>;
290*4882a593Smuzhiyun		adi,input-colorspace = "rgb";
291*4882a593Smuzhiyun		adi,input-clock = "1x";
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun		ports {
294*4882a593Smuzhiyun			#address-cells = <1>;
295*4882a593Smuzhiyun			#size-cells = <0>;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun			port@0 {
298*4882a593Smuzhiyun				reg = <0>;
299*4882a593Smuzhiyun				adv7511_in: endpoint {
300*4882a593Smuzhiyun					remote-endpoint = <&du_out_rgb0>;
301*4882a593Smuzhiyun				};
302*4882a593Smuzhiyun			};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun			port@1 {
305*4882a593Smuzhiyun				reg = <1>;
306*4882a593Smuzhiyun				adv7511_out: endpoint {
307*4882a593Smuzhiyun					remote-endpoint = <&hdmi_con>;
308*4882a593Smuzhiyun				};
309*4882a593Smuzhiyun			};
310*4882a593Smuzhiyun		};
311*4882a593Smuzhiyun	};
312*4882a593Smuzhiyun};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun&iic3 {
315*4882a593Smuzhiyun	status = "okay";
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun	pmic@58 {
318*4882a593Smuzhiyun		compatible = "dlg,da9063";
319*4882a593Smuzhiyun		reg = <0x58>;
320*4882a593Smuzhiyun		pinctrl-names = "default";
321*4882a593Smuzhiyun		pinctrl-0 = <&pmic_irq_pins>;
322*4882a593Smuzhiyun		interrupt-parent = <&irqc>;
323*4882a593Smuzhiyun		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
324*4882a593Smuzhiyun		interrupt-controller;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun		rtc {
327*4882a593Smuzhiyun			compatible = "dlg,da9063-rtc";
328*4882a593Smuzhiyun		};
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun		wdt {
331*4882a593Smuzhiyun			compatible = "dlg,da9063-watchdog";
332*4882a593Smuzhiyun		};
333*4882a593Smuzhiyun	};
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun&du {
337*4882a593Smuzhiyun	pinctrl-0 = <&du0_pins &du1_pins>;
338*4882a593Smuzhiyun	pinctrl-names = "default";
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
341*4882a593Smuzhiyun	clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
342*4882a593Smuzhiyun	status = "okay";
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun	ports {
345*4882a593Smuzhiyun		port@0 {
346*4882a593Smuzhiyun			endpoint {
347*4882a593Smuzhiyun				remote-endpoint = <&adv7511_in>;
348*4882a593Smuzhiyun			};
349*4882a593Smuzhiyun		};
350*4882a593Smuzhiyun		port@1 {
351*4882a593Smuzhiyun			endpoint {
352*4882a593Smuzhiyun				remote-endpoint = <&adv7123_in>;
353*4882a593Smuzhiyun			};
354*4882a593Smuzhiyun		};
355*4882a593Smuzhiyun	};
356*4882a593Smuzhiyun};
357