1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the Porter board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Cogent Embedded, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/* 9*4882a593Smuzhiyun * SSI-AK4642 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * JP3: 2-1: AK4642 12*4882a593Smuzhiyun * 2-3: ADV7511 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * This command is required before playback/capture: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * amixer set "LINEOUT Mixer DACL" on 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/dts-v1/; 20*4882a593Smuzhiyun#include "r8a7791.dtsi" 21*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun/ { 24*4882a593Smuzhiyun model = "Porter"; 25*4882a593Smuzhiyun compatible = "renesas,porter", "renesas,r8a7791"; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun aliases { 28*4882a593Smuzhiyun serial0 = &scif0; 29*4882a593Smuzhiyun i2c9 = &gpioi2c2; 30*4882a593Smuzhiyun i2c10 = &i2chdmi; 31*4882a593Smuzhiyun mmc0 = &sdhi0; 32*4882a593Smuzhiyun mmc1 = &sdhi2; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun chosen { 36*4882a593Smuzhiyun bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 37*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun memory@40000000 { 41*4882a593Smuzhiyun device_type = "memory"; 42*4882a593Smuzhiyun reg = <0 0x40000000 0 0x40000000>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun memory@200000000 { 46*4882a593Smuzhiyun device_type = "memory"; 47*4882a593Smuzhiyun reg = <2 0x00000000 0 0x40000000>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun vcc_sdhi0: regulator-vcc-sdhi0 { 51*4882a593Smuzhiyun compatible = "regulator-fixed"; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun regulator-name = "SDHI0 Vcc"; 54*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 55*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 56*4882a593Smuzhiyun regulator-always-on; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun vccq_sdhi0: regulator-vccq-sdhi0 { 60*4882a593Smuzhiyun compatible = "regulator-gpio"; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun regulator-name = "SDHI0 VccQ"; 63*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 64*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 67*4882a593Smuzhiyun gpios-states = <1>; 68*4882a593Smuzhiyun states = <3300000 1>, <1800000 0>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun vcc_sdhi2: regulator-vcc-sdhi2 { 72*4882a593Smuzhiyun compatible = "regulator-fixed"; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun regulator-name = "SDHI2 Vcc"; 75*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 76*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 77*4882a593Smuzhiyun regulator-always-on; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun vccq_sdhi2: regulator-vccq-sdhi2 { 81*4882a593Smuzhiyun compatible = "regulator-gpio"; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun regulator-name = "SDHI2 VccQ"; 84*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 85*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; 88*4882a593Smuzhiyun gpios-states = <1>; 89*4882a593Smuzhiyun states = <3300000 1>, <1800000 0>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun hdmi-out { 93*4882a593Smuzhiyun compatible = "hdmi-connector"; 94*4882a593Smuzhiyun type = "a"; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun port { 97*4882a593Smuzhiyun hdmi_con: endpoint { 98*4882a593Smuzhiyun remote-endpoint = <&adv7511_out>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun x3_clk: x3-clock { 104*4882a593Smuzhiyun compatible = "fixed-clock"; 105*4882a593Smuzhiyun #clock-cells = <0>; 106*4882a593Smuzhiyun clock-frequency = <148500000>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun x16_clk: x16-clock { 110*4882a593Smuzhiyun compatible = "fixed-clock"; 111*4882a593Smuzhiyun #clock-cells = <0>; 112*4882a593Smuzhiyun clock-frequency = <74250000>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun x14_clk: audio_clock { 116*4882a593Smuzhiyun compatible = "fixed-clock"; 117*4882a593Smuzhiyun #clock-cells = <0>; 118*4882a593Smuzhiyun clock-frequency = <11289600>; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun sound { 122*4882a593Smuzhiyun compatible = "simple-audio-card"; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun simple-audio-card,format = "left_j"; 125*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&soundcodec>; 126*4882a593Smuzhiyun simple-audio-card,frame-master = <&soundcodec>; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun simple-audio-card,cpu { 129*4882a593Smuzhiyun sound-dai = <&rcar_sound>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun soundcodec: simple-audio-card,codec { 133*4882a593Smuzhiyun sound-dai = <&ak4642>; 134*4882a593Smuzhiyun clocks = <&x14_clk>; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun gpioi2c2: i2c-9 { 139*4882a593Smuzhiyun #address-cells = <1>; 140*4882a593Smuzhiyun #size-cells = <0>; 141*4882a593Smuzhiyun compatible = "i2c-gpio"; 142*4882a593Smuzhiyun status = "disabled"; 143*4882a593Smuzhiyun scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 144*4882a593Smuzhiyun sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 145*4882a593Smuzhiyun i2c-gpio,delay-us = <5>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* 149*4882a593Smuzhiyun * A fallback to GPIO is provided for I2C2. 150*4882a593Smuzhiyun */ 151*4882a593Smuzhiyun i2chdmi: i2c-10 { 152*4882a593Smuzhiyun compatible = "i2c-demux-pinctrl"; 153*4882a593Smuzhiyun i2c-parent = <&i2c2>, <&gpioi2c2>; 154*4882a593Smuzhiyun i2c-bus-name = "i2c-hdmi"; 155*4882a593Smuzhiyun #address-cells = <1>; 156*4882a593Smuzhiyun #size-cells = <0>; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun ak4642: codec@12 { 159*4882a593Smuzhiyun compatible = "asahi-kasei,ak4642"; 160*4882a593Smuzhiyun #sound-dai-cells = <0>; 161*4882a593Smuzhiyun reg = <0x12>; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun composite-in@20 { 165*4882a593Smuzhiyun compatible = "adi,adv7180"; 166*4882a593Smuzhiyun reg = <0x20>; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun port { 169*4882a593Smuzhiyun adv7180: endpoint { 170*4882a593Smuzhiyun bus-width = <8>; 171*4882a593Smuzhiyun remote-endpoint = <&vin0ep>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun hdmi@39 { 177*4882a593Smuzhiyun compatible = "adi,adv7511w"; 178*4882a593Smuzhiyun reg = <0x39>; 179*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 180*4882a593Smuzhiyun interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun adi,input-depth = <8>; 183*4882a593Smuzhiyun adi,input-colorspace = "rgb"; 184*4882a593Smuzhiyun adi,input-clock = "1x"; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun ports { 187*4882a593Smuzhiyun #address-cells = <1>; 188*4882a593Smuzhiyun #size-cells = <0>; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun port@0 { 191*4882a593Smuzhiyun reg = <0>; 192*4882a593Smuzhiyun adv7511_in: endpoint { 193*4882a593Smuzhiyun remote-endpoint = <&du_out_rgb>; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun port@1 { 198*4882a593Smuzhiyun reg = <1>; 199*4882a593Smuzhiyun adv7511_out: endpoint { 200*4882a593Smuzhiyun remote-endpoint = <&hdmi_con>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun}; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun&extal_clk { 209*4882a593Smuzhiyun clock-frequency = <20000000>; 210*4882a593Smuzhiyun}; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun&pfc { 213*4882a593Smuzhiyun scif0_pins: scif0 { 214*4882a593Smuzhiyun groups = "scif0_data_d"; 215*4882a593Smuzhiyun function = "scif0"; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun ether_pins: ether { 219*4882a593Smuzhiyun groups = "eth_link", "eth_mdio", "eth_rmii"; 220*4882a593Smuzhiyun function = "eth"; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun phy1_pins: phy1 { 224*4882a593Smuzhiyun groups = "intc_irq0"; 225*4882a593Smuzhiyun function = "intc"; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun pmic_irq_pins: pmicirq { 229*4882a593Smuzhiyun groups = "intc_irq2"; 230*4882a593Smuzhiyun function = "intc"; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun sdhi0_pins: sd0 { 234*4882a593Smuzhiyun groups = "sdhi0_data4", "sdhi0_ctrl"; 235*4882a593Smuzhiyun function = "sdhi0"; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun sdhi2_pins: sd2 { 239*4882a593Smuzhiyun groups = "sdhi2_data4", "sdhi2_ctrl"; 240*4882a593Smuzhiyun function = "sdhi2"; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun qspi_pins: qspi { 244*4882a593Smuzhiyun groups = "qspi_ctrl", "qspi_data4"; 245*4882a593Smuzhiyun function = "qspi"; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun i2c2_pins: i2c2 { 249*4882a593Smuzhiyun groups = "i2c2"; 250*4882a593Smuzhiyun function = "i2c2"; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun usb0_pins: usb0 { 254*4882a593Smuzhiyun groups = "usb0"; 255*4882a593Smuzhiyun function = "usb0"; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun usb1_pins: usb1 { 259*4882a593Smuzhiyun groups = "usb1"; 260*4882a593Smuzhiyun function = "usb1"; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun vin0_pins: vin0 { 264*4882a593Smuzhiyun groups = "vin0_data8", "vin0_clk"; 265*4882a593Smuzhiyun function = "vin0"; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun can0_pins: can0 { 269*4882a593Smuzhiyun groups = "can0_data"; 270*4882a593Smuzhiyun function = "can0"; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun du_pins: du { 274*4882a593Smuzhiyun groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; 275*4882a593Smuzhiyun function = "du"; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun ssi_pins: sound { 279*4882a593Smuzhiyun groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; 280*4882a593Smuzhiyun function = "ssi"; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun audio_clk_pins: audio_clk { 284*4882a593Smuzhiyun groups = "audio_clk_a"; 285*4882a593Smuzhiyun function = "audio_clk"; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun}; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun&scif0 { 290*4882a593Smuzhiyun pinctrl-0 = <&scif0_pins>; 291*4882a593Smuzhiyun pinctrl-names = "default"; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun status = "okay"; 294*4882a593Smuzhiyun}; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyunðer { 297*4882a593Smuzhiyun pinctrl-0 = <ðer_pins &phy1_pins>; 298*4882a593Smuzhiyun pinctrl-names = "default"; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun phy-handle = <&phy1>; 301*4882a593Smuzhiyun renesas,ether-link-active-low; 302*4882a593Smuzhiyun status = "okay"; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun phy1: ethernet-phy@1 { 305*4882a593Smuzhiyun reg = <1>; 306*4882a593Smuzhiyun interrupt-parent = <&irqc0>; 307*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 308*4882a593Smuzhiyun micrel,led-mode = <1>; 309*4882a593Smuzhiyun reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun}; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun&sdhi0 { 314*4882a593Smuzhiyun pinctrl-0 = <&sdhi0_pins>; 315*4882a593Smuzhiyun pinctrl-names = "default"; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun vmmc-supply = <&vcc_sdhi0>; 318*4882a593Smuzhiyun vqmmc-supply = <&vccq_sdhi0>; 319*4882a593Smuzhiyun cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; 320*4882a593Smuzhiyun wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; 321*4882a593Smuzhiyun status = "okay"; 322*4882a593Smuzhiyun}; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun&sdhi2 { 325*4882a593Smuzhiyun pinctrl-0 = <&sdhi2_pins>; 326*4882a593Smuzhiyun pinctrl-names = "default"; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun vmmc-supply = <&vcc_sdhi2>; 329*4882a593Smuzhiyun vqmmc-supply = <&vccq_sdhi2>; 330*4882a593Smuzhiyun cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; 331*4882a593Smuzhiyun status = "okay"; 332*4882a593Smuzhiyun}; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun&qspi { 335*4882a593Smuzhiyun pinctrl-0 = <&qspi_pins>; 336*4882a593Smuzhiyun pinctrl-names = "default"; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun status = "okay"; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun flash@0 { 341*4882a593Smuzhiyun compatible = "spansion,s25fl512s", "jedec,spi-nor"; 342*4882a593Smuzhiyun reg = <0>; 343*4882a593Smuzhiyun spi-max-frequency = <30000000>; 344*4882a593Smuzhiyun spi-tx-bus-width = <4>; 345*4882a593Smuzhiyun spi-rx-bus-width = <4>; 346*4882a593Smuzhiyun m25p,fast-read; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun partitions { 349*4882a593Smuzhiyun compatible = "fixed-partitions"; 350*4882a593Smuzhiyun #address-cells = <1>; 351*4882a593Smuzhiyun #size-cells = <1>; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun partition@0 { 354*4882a593Smuzhiyun label = "loader_prg"; 355*4882a593Smuzhiyun reg = <0x00000000 0x00040000>; 356*4882a593Smuzhiyun read-only; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun partition@40000 { 359*4882a593Smuzhiyun label = "user_prg"; 360*4882a593Smuzhiyun reg = <0x00040000 0x00400000>; 361*4882a593Smuzhiyun read-only; 362*4882a593Smuzhiyun }; 363*4882a593Smuzhiyun partition@440000 { 364*4882a593Smuzhiyun label = "flash_fs"; 365*4882a593Smuzhiyun reg = <0x00440000 0x03bc0000>; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun}; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun&i2c2 { 372*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 373*4882a593Smuzhiyun pinctrl-names = "i2c-hdmi"; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun clock-frequency = <400000>; 376*4882a593Smuzhiyun}; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun&i2c6 { 379*4882a593Smuzhiyun pinctrl-names = "default"; 380*4882a593Smuzhiyun pinctrl-0 = <&pmic_irq_pins>; 381*4882a593Smuzhiyun status = "okay"; 382*4882a593Smuzhiyun clock-frequency = <100000>; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun pmic@5a { 385*4882a593Smuzhiyun compatible = "dlg,da9063l"; 386*4882a593Smuzhiyun reg = <0x5a>; 387*4882a593Smuzhiyun interrupt-parent = <&irqc0>; 388*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 389*4882a593Smuzhiyun interrupt-controller; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun wdt { 392*4882a593Smuzhiyun compatible = "dlg,da9063-watchdog"; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun vdd_dvfs: regulator@68 { 397*4882a593Smuzhiyun compatible = "dlg,da9210"; 398*4882a593Smuzhiyun reg = <0x68>; 399*4882a593Smuzhiyun interrupt-parent = <&irqc0>; 400*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 403*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 404*4882a593Smuzhiyun regulator-boot-on; 405*4882a593Smuzhiyun regulator-always-on; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun}; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun&sata0 { 410*4882a593Smuzhiyun status = "okay"; 411*4882a593Smuzhiyun}; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun&cpu0 { 414*4882a593Smuzhiyun cpu0-supply = <&vdd_dvfs>; 415*4882a593Smuzhiyun}; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun/* composite video input */ 418*4882a593Smuzhiyun&vin0 { 419*4882a593Smuzhiyun status = "okay"; 420*4882a593Smuzhiyun pinctrl-0 = <&vin0_pins>; 421*4882a593Smuzhiyun pinctrl-names = "default"; 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun port { 424*4882a593Smuzhiyun vin0ep: endpoint { 425*4882a593Smuzhiyun remote-endpoint = <&adv7180>; 426*4882a593Smuzhiyun bus-width = <8>; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun }; 429*4882a593Smuzhiyun}; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun&pci0 { 432*4882a593Smuzhiyun pinctrl-0 = <&usb0_pins>; 433*4882a593Smuzhiyun pinctrl-names = "default"; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun status = "okay"; 436*4882a593Smuzhiyun}; 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun&pci1 { 439*4882a593Smuzhiyun pinctrl-0 = <&usb1_pins>; 440*4882a593Smuzhiyun pinctrl-names = "default"; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun status = "okay"; 443*4882a593Smuzhiyun}; 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun&hsusb { 446*4882a593Smuzhiyun pinctrl-0 = <&usb0_pins>; 447*4882a593Smuzhiyun pinctrl-names = "default"; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun status = "okay"; 450*4882a593Smuzhiyun}; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun&usbphy { 453*4882a593Smuzhiyun status = "okay"; 454*4882a593Smuzhiyun}; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun&pcie_bus_clk { 457*4882a593Smuzhiyun clock-frequency = <100000000>; 458*4882a593Smuzhiyun}; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun&pciec { 461*4882a593Smuzhiyun status = "okay"; 462*4882a593Smuzhiyun}; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun&can0 { 465*4882a593Smuzhiyun pinctrl-0 = <&can0_pins>; 466*4882a593Smuzhiyun pinctrl-names = "default"; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun status = "okay"; 469*4882a593Smuzhiyun}; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun&du { 472*4882a593Smuzhiyun pinctrl-0 = <&du_pins>; 473*4882a593Smuzhiyun pinctrl-names = "default"; 474*4882a593Smuzhiyun status = "okay"; 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 477*4882a593Smuzhiyun <&x3_clk>, <&x16_clk>; 478*4882a593Smuzhiyun clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun ports { 481*4882a593Smuzhiyun port@0 { 482*4882a593Smuzhiyun endpoint { 483*4882a593Smuzhiyun remote-endpoint = <&adv7511_in>; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun }; 486*4882a593Smuzhiyun }; 487*4882a593Smuzhiyun}; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun&lvds0 { 490*4882a593Smuzhiyun ports { 491*4882a593Smuzhiyun port@1 { 492*4882a593Smuzhiyun lvds_connector: endpoint { 493*4882a593Smuzhiyun }; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun}; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun&rcar_sound { 499*4882a593Smuzhiyun pinctrl-0 = <&ssi_pins &audio_clk_pins>; 500*4882a593Smuzhiyun pinctrl-names = "default"; 501*4882a593Smuzhiyun status = "okay"; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun /* Single DAI */ 504*4882a593Smuzhiyun #sound-dai-cells = <0>; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun rcar_sound,dai { 507*4882a593Smuzhiyun dai0 { 508*4882a593Smuzhiyun playback = <&ssi0>; 509*4882a593Smuzhiyun capture = <&ssi1>; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun}; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun&rwdt { 515*4882a593Smuzhiyun timeout-sec = <60>; 516*4882a593Smuzhiyun status = "okay"; 517*4882a593Smuzhiyun}; 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun&ssi1 { 520*4882a593Smuzhiyun shared-pin; 521*4882a593Smuzhiyun}; 522