1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the SK-RZG1E board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016-2017 Cogent Embedded, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun#include "r8a7745.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "SK-RZG1E"; 13*4882a593Smuzhiyun compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun serial0 = &scif2; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun chosen { 20*4882a593Smuzhiyun bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 21*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun memory@40000000 { 25*4882a593Smuzhiyun device_type = "memory"; 26*4882a593Smuzhiyun reg = <0 0x40000000 0 0x40000000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&extal_clk { 31*4882a593Smuzhiyun clock-frequency = <20000000>; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&pfc { 35*4882a593Smuzhiyun scif2_pins: scif2 { 36*4882a593Smuzhiyun groups = "scif2_data"; 37*4882a593Smuzhiyun function = "scif2"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun ether_pins: ether { 41*4882a593Smuzhiyun groups = "eth_link", "eth_mdio", "eth_rmii"; 42*4882a593Smuzhiyun function = "eth"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun phy1_pins: phy1 { 46*4882a593Smuzhiyun groups = "intc_irq8"; 47*4882a593Smuzhiyun function = "intc"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&scif2 { 52*4882a593Smuzhiyun pinctrl-0 = <&scif2_pins>; 53*4882a593Smuzhiyun pinctrl-names = "default"; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun status = "okay"; 56*4882a593Smuzhiyun}; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunðer { 59*4882a593Smuzhiyun pinctrl-0 = <ðer_pins &phy1_pins>; 60*4882a593Smuzhiyun pinctrl-names = "default"; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun phy-handle = <&phy1>; 63*4882a593Smuzhiyun renesas,ether-link-active-low; 64*4882a593Smuzhiyun status = "okay"; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun phy1: ethernet-phy@1 { 67*4882a593Smuzhiyun reg = <1>; 68*4882a593Smuzhiyun interrupt-parent = <&irqc>; 69*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 70*4882a593Smuzhiyun micrel,led-mode = <1>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun}; 73