1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the iWave RZ/G1N Qseven SOM 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics Corp. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "r8a7744.dtsi" 9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun compatible = "iwave,g20m", "renesas,r8a7744"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun memory@40000000 { 15*4882a593Smuzhiyun device_type = "memory"; 16*4882a593Smuzhiyun reg = <0 0x40000000 0 0x40000000>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun reg_3p3v: 3p3v { 20*4882a593Smuzhiyun compatible = "regulator-fixed"; 21*4882a593Smuzhiyun regulator-name = "3P3V"; 22*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 23*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 24*4882a593Smuzhiyun regulator-always-on; 25*4882a593Smuzhiyun regulator-boot-on; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&extal_clk { 30*4882a593Smuzhiyun clock-frequency = <20000000>; 31*4882a593Smuzhiyun}; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun&pfc { 34*4882a593Smuzhiyun mmcif0_pins: mmc { 35*4882a593Smuzhiyun groups = "mmc_data8_b", "mmc_ctrl"; 36*4882a593Smuzhiyun function = "mmc"; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun qspi_pins: qspi { 40*4882a593Smuzhiyun groups = "qspi_ctrl", "qspi_data2"; 41*4882a593Smuzhiyun function = "qspi"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun sdhi0_pins: sd0 { 45*4882a593Smuzhiyun groups = "sdhi0_data4", "sdhi0_ctrl"; 46*4882a593Smuzhiyun function = "sdhi0"; 47*4882a593Smuzhiyun power-source = <3300>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&mmcif0 { 52*4882a593Smuzhiyun pinctrl-0 = <&mmcif0_pins>; 53*4882a593Smuzhiyun pinctrl-names = "default"; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 56*4882a593Smuzhiyun bus-width = <8>; 57*4882a593Smuzhiyun non-removable; 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&qspi { 62*4882a593Smuzhiyun pinctrl-0 = <&qspi_pins>; 63*4882a593Smuzhiyun pinctrl-names = "default"; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* WARNING - This device contains the bootloader. Handle with care. */ 68*4882a593Smuzhiyun flash: flash@0 { 69*4882a593Smuzhiyun #address-cells = <1>; 70*4882a593Smuzhiyun #size-cells = <1>; 71*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 72*4882a593Smuzhiyun reg = <0>; 73*4882a593Smuzhiyun spi-max-frequency = <50000000>; 74*4882a593Smuzhiyun spi-tx-bus-width = <2>; 75*4882a593Smuzhiyun spi-rx-bus-width = <2>; 76*4882a593Smuzhiyun m25p,fast-read; 77*4882a593Smuzhiyun spi-cpol; 78*4882a593Smuzhiyun spi-cpha; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&sdhi0 { 83*4882a593Smuzhiyun pinctrl-0 = <&sdhi0_pins>; 84*4882a593Smuzhiyun pinctrl-names = "default"; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 87*4882a593Smuzhiyun vqmmc-supply = <®_3p3v>; 88*4882a593Smuzhiyun cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; 89*4882a593Smuzhiyun status = "okay"; 90*4882a593Smuzhiyun}; 91