1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the Genmai board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013-14 Renesas Solutions Corp. 6*4882a593Smuzhiyun * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun#include "r7s72100.dtsi" 11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 12*4882a593Smuzhiyun#include <dt-bindings/pinctrl/r7s72100-pinctrl.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "Genmai"; 16*4882a593Smuzhiyun compatible = "renesas,genmai", "renesas,r7s72100"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun aliases { 19*4882a593Smuzhiyun serial0 = &scif2; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun chosen { 23*4882a593Smuzhiyun bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 24*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun memory@8000000 { 28*4882a593Smuzhiyun device_type = "memory"; 29*4882a593Smuzhiyun reg = <0x08000000 0x08000000>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun lbsc { 33*4882a593Smuzhiyun #address-cells = <1>; 34*4882a593Smuzhiyun #size-cells = <1>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun leds { 38*4882a593Smuzhiyun status = "okay"; 39*4882a593Smuzhiyun compatible = "gpio-leds"; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun led1 { 42*4882a593Smuzhiyun gpios = <&port4 10 GPIO_ACTIVE_LOW>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun led2 { 46*4882a593Smuzhiyun gpios = <&port4 11 GPIO_ACTIVE_LOW>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&pinctrl { 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun scif2_pins: serial2 { 54*4882a593Smuzhiyun /* P3_0 as TxD2; P3_2 as RxD2 */ 55*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun i2c2_pins: i2c2 { 59*4882a593Smuzhiyun /* RIIC2: P1_4 as SCL, P1_5 as SDA */ 60*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun ether_pins: ether { 64*4882a593Smuzhiyun /* Ethernet on Ports 1,2,3,5 */ 65*4882a593Smuzhiyun pinmux = <RZA1_PINMUX(1, 14, 4)>,/* P1_14 = ET_COL */ 66*4882a593Smuzhiyun <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */ 67*4882a593Smuzhiyun <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */ 68*4882a593Smuzhiyun <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */ 69*4882a593Smuzhiyun <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */ 70*4882a593Smuzhiyun <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */ 71*4882a593Smuzhiyun <RZA1_PINMUX(2, 0, 2)>, /* P2_0 = ET_TXCLK */ 72*4882a593Smuzhiyun <RZA1_PINMUX(2, 1, 2)>, /* P2_1 = ET_TXER */ 73*4882a593Smuzhiyun <RZA1_PINMUX(2, 2, 2)>, /* P2_2 = ET_TXEN */ 74*4882a593Smuzhiyun <RZA1_PINMUX(2, 3, 2)>, /* P2_3 = ET_CRS */ 75*4882a593Smuzhiyun <RZA1_PINMUX(2, 4, 2)>, /* P2_4 = ET_TXD0 */ 76*4882a593Smuzhiyun <RZA1_PINMUX(2, 5, 2)>, /* P2_5 = ET_TXD1 */ 77*4882a593Smuzhiyun <RZA1_PINMUX(2, 6, 2)>, /* P2_6 = ET_TXD2 */ 78*4882a593Smuzhiyun <RZA1_PINMUX(2, 7, 2)>, /* P2_7 = ET_TXD3 */ 79*4882a593Smuzhiyun <RZA1_PINMUX(2, 8, 2)>, /* P2_8 = ET_RXD0 */ 80*4882a593Smuzhiyun <RZA1_PINMUX(2, 9, 2)>, /* P2_9 = ET_RXD1 */ 81*4882a593Smuzhiyun <RZA1_PINMUX(2, 10, 2)>,/* P2_10 = ET_RXD2 */ 82*4882a593Smuzhiyun <RZA1_PINMUX(2, 11, 2)>;/* P2_11 = ET_RXD3 */ 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&extal_clk { 87*4882a593Smuzhiyun clock-frequency = <13330000>; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&usb_x1_clk { 91*4882a593Smuzhiyun clock-frequency = <48000000>; 92*4882a593Smuzhiyun}; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun&rtc_x1_clk { 95*4882a593Smuzhiyun clock-frequency = <32768>; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&mtu2 { 99*4882a593Smuzhiyun status = "okay"; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyunðer { 103*4882a593Smuzhiyun pinctrl-names = "default"; 104*4882a593Smuzhiyun pinctrl-0 = <ðer_pins>; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun renesas,no-ether-link; 109*4882a593Smuzhiyun phy-handle = <&phy0>; 110*4882a593Smuzhiyun phy0: ethernet-phy@0 { 111*4882a593Smuzhiyun reg = <0>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun&i2c2 { 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun clock-frequency = <400000>; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun pinctrl-names = "default"; 120*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun eeprom@50 { 123*4882a593Smuzhiyun compatible = "renesas,r1ex24128", "atmel,24c128"; 124*4882a593Smuzhiyun reg = <0x50>; 125*4882a593Smuzhiyun pagesize = <64>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun}; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun&rtc { 130*4882a593Smuzhiyun status = "okay"; 131*4882a593Smuzhiyun}; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun&scif2 { 134*4882a593Smuzhiyun pinctrl-names = "default"; 135*4882a593Smuzhiyun pinctrl-0 = <&scif2_pins>; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&spi4 { 141*4882a593Smuzhiyun status = "okay"; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun codec: codec@0 { 144*4882a593Smuzhiyun compatible = "wlf,wm8978"; 145*4882a593Smuzhiyun reg = <0>; 146*4882a593Smuzhiyun spi-max-frequency = <5000000>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun}; 149