1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun#include "pxa2xx.dtsi" 6*4882a593Smuzhiyun#include "dt-bindings/clock/pxa-clock.h" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun model = "Marvell PXA25x family SoC"; 10*4882a593Smuzhiyun compatible = "marvell,pxa250"; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun clocks { 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * The muxing of external clocks/internal dividers for osc* clock 15*4882a593Smuzhiyun * sources has been hidden under the carpet by now. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #address-cells = <1>; 18*4882a593Smuzhiyun #size-cells = <1>; 19*4882a593Smuzhiyun ranges; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun clks: pxa2xx_clks@41300004 { 22*4882a593Smuzhiyun compatible = "marvell,pxa250-core-clocks"; 23*4882a593Smuzhiyun #clock-cells = <1>; 24*4882a593Smuzhiyun status = "okay"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* timer oscillator */ 28*4882a593Smuzhiyun clktimer: oscillator { 29*4882a593Smuzhiyun compatible = "fixed-clock"; 30*4882a593Smuzhiyun #clock-cells = <0>; 31*4882a593Smuzhiyun clock-frequency = <3686400>; 32*4882a593Smuzhiyun clock-output-names = "ostimer"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun pxabus { 37*4882a593Smuzhiyun pdma: dma-controller@40000000 { 38*4882a593Smuzhiyun compatible = "marvell,pdma-1.0"; 39*4882a593Smuzhiyun reg = <0x40000000 0x10000>; 40*4882a593Smuzhiyun interrupts = <25>; 41*4882a593Smuzhiyun #dma-channels = <16>; 42*4882a593Smuzhiyun #dma-cells = <2>; 43*4882a593Smuzhiyun #dma-requests = <40>; 44*4882a593Smuzhiyun status = "okay"; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun pxairq: interrupt-controller@40d00000 { 48*4882a593Smuzhiyun marvell,intc-priority; 49*4882a593Smuzhiyun marvell,intc-nr-irqs = <32>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun pinctrl: pinctrl@40e00000 { 53*4882a593Smuzhiyun reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 54*4882a593Smuzhiyun 0x40f00020 0x10>; 55*4882a593Smuzhiyun compatible = "marvell,pxa25x-pinctrl"; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun gpio: gpio@40e00000 { 59*4882a593Smuzhiyun compatible = "intel,pxa25x-gpio"; 60*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 0 84>; 61*4882a593Smuzhiyun clocks = <&clks CLK_NONE>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun pwm0: pwm@40b00000 { 65*4882a593Smuzhiyun compatible = "marvell,pxa250-pwm"; 66*4882a593Smuzhiyun reg = <0x40b00000 0x10>; 67*4882a593Smuzhiyun #pwm-cells = <1>; 68*4882a593Smuzhiyun clocks = <&clks CLK_PWM0>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun pwm1: pwm@40b00010 { 72*4882a593Smuzhiyun compatible = "marvell,pxa250-pwm"; 73*4882a593Smuzhiyun reg = <0x40b00010 0x10>; 74*4882a593Smuzhiyun #pwm-cells = <1>; 75*4882a593Smuzhiyun clocks = <&clks CLK_PWM1>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun rtc@40900000 { 79*4882a593Smuzhiyun clocks = <&clks CLK_OSC32k768>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun timer@40a00000 { 84*4882a593Smuzhiyun compatible = "marvell,pxa-timer"; 85*4882a593Smuzhiyun reg = <0x40a00000 0x20>; 86*4882a593Smuzhiyun interrupts = <26>; 87*4882a593Smuzhiyun clocks = <&clktimer>; 88*4882a593Smuzhiyun status = "okay"; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun pxa250_opp_table: opp_table0 { 92*4882a593Smuzhiyun compatible = "operating-points-v2"; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun opp-99532800 { 95*4882a593Smuzhiyun opp-hz = /bits/ 64 <99532800>; 96*4882a593Smuzhiyun opp-microvolt = <1000000 950000 1650000>; 97*4882a593Smuzhiyun clock-latency-ns = <20>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun opp-199065600 { 100*4882a593Smuzhiyun opp-hz = /bits/ 64 <199065600>; 101*4882a593Smuzhiyun opp-microvolt = <1000000 950000 1650000>; 102*4882a593Smuzhiyun clock-latency-ns = <20>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun opp-298598400 { 105*4882a593Smuzhiyun opp-hz = /bits/ 64 <298598400>; 106*4882a593Smuzhiyun opp-microvolt = <1100000 1045000 1650000>; 107*4882a593Smuzhiyun clock-latency-ns = <20>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun opp-398131200 { 110*4882a593Smuzhiyun opp-hz = /bits/ 64 <398131200>; 111*4882a593Smuzhiyun opp-microvolt = <1300000 1235000 1650000>; 112*4882a593Smuzhiyun clock-latency-ns = <20>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun}; 116