1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "omap3-gta04a5.dts" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun&omap3_pmx_core { 9*4882a593Smuzhiyun model = "Goldelico GTA04A5/Letux 2804 with OneNAND"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun gpmc_pins: pinmux_gpmc_pins { 12*4882a593Smuzhiyun pinctrl-single,pins = < 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* address lines */ 15*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ 16*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ 17*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* data lines, gpmc_d0..d7 not muxable according to TRM */ 20*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ 21*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ 22*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ 23*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ 24*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ 25*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ 26*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ 27*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable 31*4882a593Smuzhiyun * according to TRM. OneNAND seems to require PIN_INPUT on clock. 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ 34*4882a593Smuzhiyun OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ 35*4882a593Smuzhiyun >; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&gpmc { 40*4882a593Smuzhiyun /* switch inherited setup to OneNAND */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ 43*4882a593Smuzhiyun pinctrl-names = "default"; 44*4882a593Smuzhiyun pinctrl-0 = <&gpmc_pins>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /delete-node/ nand@0,0; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun onenand@0,0 { 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #address-cells = <1>; 51*4882a593Smuzhiyun #size-cells = <1>; 52*4882a593Smuzhiyun compatible = "ti,omap2-onenand"; 53*4882a593Smuzhiyun reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun gpmc,sync-read; 56*4882a593Smuzhiyun gpmc,sync-write; 57*4882a593Smuzhiyun gpmc,burst-length = <16>; 58*4882a593Smuzhiyun gpmc,burst-read; 59*4882a593Smuzhiyun gpmc,burst-wrap; 60*4882a593Smuzhiyun gpmc,burst-write; 61*4882a593Smuzhiyun gpmc,device-width = <2>; 62*4882a593Smuzhiyun gpmc,mux-add-data = <2>; 63*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 64*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <87>; 65*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <87>; 66*4882a593Smuzhiyun gpmc,adv-on-ns = <0>; 67*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <10>; 68*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <10>; 69*4882a593Smuzhiyun gpmc,oe-on-ns = <15>; 70*4882a593Smuzhiyun gpmc,oe-off-ns = <87>; 71*4882a593Smuzhiyun gpmc,we-on-ns = <0>; 72*4882a593Smuzhiyun gpmc,we-off-ns = <87>; 73*4882a593Smuzhiyun gpmc,rd-cycle-ns = <112>; 74*4882a593Smuzhiyun gpmc,wr-cycle-ns = <112>; 75*4882a593Smuzhiyun gpmc,access-ns = <81>; 76*4882a593Smuzhiyun gpmc,page-burst-access-ns = <15>; 77*4882a593Smuzhiyun gpmc,bus-turnaround-ns = <0>; 78*4882a593Smuzhiyun gpmc,cycle2cycle-delay-ns = <0>; 79*4882a593Smuzhiyun gpmc,wait-monitoring-ns = <0>; 80*4882a593Smuzhiyun gpmc,clk-activation-ns = <5>; 81*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <30>; 82*4882a593Smuzhiyun gpmc,wr-access-ns = <81>; 83*4882a593Smuzhiyun gpmc,sync-clk-ps = <15000>; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun x-loader@0 { 86*4882a593Smuzhiyun label = "X-Loader"; 87*4882a593Smuzhiyun reg = <0 0x80000>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun bootloaders@80000 { 91*4882a593Smuzhiyun label = "U-Boot"; 92*4882a593Smuzhiyun reg = <0x80000 0x1c0000>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun bootloaders_env@240000 { 96*4882a593Smuzhiyun label = "U-Boot Env"; 97*4882a593Smuzhiyun reg = <0x240000 0x40000>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun kernel@280000 { 101*4882a593Smuzhiyun label = "Kernel"; 102*4882a593Smuzhiyun reg = <0x280000 0x600000>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun filesystem@880000 { 106*4882a593Smuzhiyun label = "File System"; 107*4882a593Smuzhiyun reg = <0x880000 0>; /* 0 = MTDPART_SIZ_FULL */ 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun}; 112