1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun #address-cells = <1>; 11*4882a593Smuzhiyun #size-cells = <1>; 12*4882a593Smuzhiyun compatible = "moxa,moxart"; 13*4882a593Smuzhiyun model = "MOXART"; 14*4882a593Smuzhiyun interrupt-parent = <&intc>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun cpus { 17*4882a593Smuzhiyun #address-cells = <1>; 18*4882a593Smuzhiyun #size-cells = <0>; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun cpu@0 { 21*4882a593Smuzhiyun device_type = "cpu"; 22*4882a593Smuzhiyun compatible = "faraday,fa526"; 23*4882a593Smuzhiyun reg = <0>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun clocks { 28*4882a593Smuzhiyun #address-cells = <1>; 29*4882a593Smuzhiyun #size-cells = <0>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun soc { 33*4882a593Smuzhiyun compatible = "simple-bus"; 34*4882a593Smuzhiyun #address-cells = <1>; 35*4882a593Smuzhiyun #size-cells = <1>; 36*4882a593Smuzhiyun reg = <0x90000000 0x10000000>; 37*4882a593Smuzhiyun ranges; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun intc: interrupt-controller@98800000 { 40*4882a593Smuzhiyun compatible = "moxa,moxart-ic", "faraday,ftintc010"; 41*4882a593Smuzhiyun reg = <0x98800000 0x100>; 42*4882a593Smuzhiyun interrupt-controller; 43*4882a593Smuzhiyun #interrupt-cells = <2>; 44*4882a593Smuzhiyun interrupt-mask = <0x00080000>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun clk_pll: clk_pll@98100000 { 48*4882a593Smuzhiyun compatible = "moxa,moxart-pll-clock"; 49*4882a593Smuzhiyun #clock-cells = <0>; 50*4882a593Smuzhiyun reg = <0x98100000 0x34>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun clk_apb: clk_apb@98100000 { 54*4882a593Smuzhiyun compatible = "moxa,moxart-apb-clock"; 55*4882a593Smuzhiyun #clock-cells = <0>; 56*4882a593Smuzhiyun reg = <0x98100000 0x34>; 57*4882a593Smuzhiyun clocks = <&clk_pll>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun timer: timer@98400000 { 61*4882a593Smuzhiyun compatible = "moxa,moxart-timer", "faraday,fttmr010"; 62*4882a593Smuzhiyun reg = <0x98400000 0x42>; 63*4882a593Smuzhiyun interrupts = <19 IRQ_TYPE_EDGE_FALLING>; 64*4882a593Smuzhiyun clocks = <&clk_apb>; 65*4882a593Smuzhiyun clock-names = "PCLK"; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun gpio: gpio@98700000 { 69*4882a593Smuzhiyun gpio-controller; 70*4882a593Smuzhiyun #gpio-cells = <2>; 71*4882a593Smuzhiyun compatible = "moxa,moxart-gpio", "faraday,ftgpio010"; 72*4882a593Smuzhiyun reg = <0x98700000 0x100>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun rtc: rtc { 76*4882a593Smuzhiyun compatible = "moxa,moxart-rtc"; 77*4882a593Smuzhiyun gpio-rtc-sclk = <&gpio 5 0>; 78*4882a593Smuzhiyun gpio-rtc-data = <&gpio 6 0>; 79*4882a593Smuzhiyun gpio-rtc-reset = <&gpio 7 0>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun dma: dma@90500000 { 83*4882a593Smuzhiyun compatible = "moxa,moxart-dma"; 84*4882a593Smuzhiyun reg = <0x90500080 0x40>; 85*4882a593Smuzhiyun interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 86*4882a593Smuzhiyun #dma-cells = <1>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun watchdog: watchdog@98500000 { 90*4882a593Smuzhiyun compatible = "moxa,moxart-watchdog", "faraday,ftwdt010"; 91*4882a593Smuzhiyun reg = <0x98500000 0x10>; 92*4882a593Smuzhiyun clocks = <&clk_apb>; 93*4882a593Smuzhiyun clock-names = "PCLK"; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun mmc: mmc@98e00000 { 97*4882a593Smuzhiyun compatible = "moxa,moxart-mmc"; 98*4882a593Smuzhiyun reg = <0x98e00000 0x5C>; 99*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 100*4882a593Smuzhiyun clocks = <&clk_apb>; 101*4882a593Smuzhiyun dmas = <&dma 5>, 102*4882a593Smuzhiyun <&dma 5>; 103*4882a593Smuzhiyun dma-names = "tx", "rx"; 104*4882a593Smuzhiyun status = "disabled"; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun mdio0: mdio@90900090 { 108*4882a593Smuzhiyun compatible = "moxa,moxart-mdio"; 109*4882a593Smuzhiyun reg = <0x90900090 0x8>; 110*4882a593Smuzhiyun #address-cells = <1>; 111*4882a593Smuzhiyun #size-cells = <0>; 112*4882a593Smuzhiyun status = "disabled"; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun mdio1: mdio@92000090 { 116*4882a593Smuzhiyun compatible = "moxa,moxart-mdio"; 117*4882a593Smuzhiyun reg = <0x92000090 0x8>; 118*4882a593Smuzhiyun #address-cells = <1>; 119*4882a593Smuzhiyun #size-cells = <0>; 120*4882a593Smuzhiyun status = "disabled"; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun mac0: mac@90900000 { 124*4882a593Smuzhiyun compatible = "moxa,moxart-mac"; 125*4882a593Smuzhiyun reg = <0x90900000 0x90>; 126*4882a593Smuzhiyun interrupts = <25 IRQ_TYPE_LEVEL_HIGH>; 127*4882a593Smuzhiyun phy-handle = <ðphy0>; 128*4882a593Smuzhiyun phy-mode = "mii"; 129*4882a593Smuzhiyun status = "disabled"; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun mac1: mac@92000000 { 133*4882a593Smuzhiyun compatible = "moxa,moxart-mac"; 134*4882a593Smuzhiyun reg = <0x92000000 0x90>; 135*4882a593Smuzhiyun interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 136*4882a593Smuzhiyun phy-handle = <ðphy1>; 137*4882a593Smuzhiyun phy-mode = "mii"; 138*4882a593Smuzhiyun status = "disabled"; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun uart0: uart@98200000 { 142*4882a593Smuzhiyun compatible = "ns16550a"; 143*4882a593Smuzhiyun reg = <0x98200000 0x20>; 144*4882a593Smuzhiyun interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; 145*4882a593Smuzhiyun reg-shift = <2>; 146*4882a593Smuzhiyun reg-io-width = <4>; 147*4882a593Smuzhiyun clock-frequency = <14745600>; 148*4882a593Smuzhiyun status = "disabled"; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun}; 152