xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/lpc4350-hitex-eval.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Hitex LPC4350 Evaluation Board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This code is released using a dual license strategy: BSD/GPL
7*4882a593Smuzhiyun * You can choose the licence that better fits your requirements.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Released under the terms of 3-clause BSD License
10*4882a593Smuzhiyun * Released under the terms of GNU General Public License Version 2.0
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun/dts-v1/;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun#include "lpc18xx.dtsi"
16*4882a593Smuzhiyun#include "lpc4350.dtsi"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun#include "dt-bindings/input/input.h"
19*4882a593Smuzhiyun#include "dt-bindings/gpio/gpio.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun/ {
22*4882a593Smuzhiyun	model = "Hitex LPC4350 Evaluation Board";
23*4882a593Smuzhiyun	compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	aliases {
26*4882a593Smuzhiyun		serial0 = &uart0;
27*4882a593Smuzhiyun		serial1 = &uart1;
28*4882a593Smuzhiyun		serial2 = &uart2;
29*4882a593Smuzhiyun		serial3 = &uart3;
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	chosen {
33*4882a593Smuzhiyun		stdout-path = &uart0;
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	memory@28000000 {
37*4882a593Smuzhiyun		device_type = "memory";
38*4882a593Smuzhiyun		reg = <0x28000000 0x800000>; /* 8 MB */
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	pca_buttons {
42*4882a593Smuzhiyun		compatible = "gpio-keys-polled";
43*4882a593Smuzhiyun		poll-interval = <100>;
44*4882a593Smuzhiyun		autorepeat;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		button0 {
47*4882a593Smuzhiyun			label = "joy:right";
48*4882a593Smuzhiyun			linux,code = <KEY_RIGHT>;
49*4882a593Smuzhiyun			gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>;
50*4882a593Smuzhiyun		};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun		button1 {
53*4882a593Smuzhiyun			label = "joy:up";
54*4882a593Smuzhiyun			linux,code = <KEY_UP>;
55*4882a593Smuzhiyun			gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>;
56*4882a593Smuzhiyun		};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun		button2 {
60*4882a593Smuzhiyun			label = "joy:enter";
61*4882a593Smuzhiyun			linux,code = <KEY_ENTER>;
62*4882a593Smuzhiyun			gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>;
63*4882a593Smuzhiyun		};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		button3 {
66*4882a593Smuzhiyun			label = "joy:left";
67*4882a593Smuzhiyun			linux,code = <KEY_LEFT>;
68*4882a593Smuzhiyun			gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>;
69*4882a593Smuzhiyun		};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun		button4 {
72*4882a593Smuzhiyun			label = "joy:down";
73*4882a593Smuzhiyun			linux,code = <KEY_DOWN>;
74*4882a593Smuzhiyun			gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>;
75*4882a593Smuzhiyun		};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun		button5 {
78*4882a593Smuzhiyun			label = "user:sw3";
79*4882a593Smuzhiyun			linux,code = <KEY_F1>;
80*4882a593Smuzhiyun			gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>;
81*4882a593Smuzhiyun		};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun		button6 {
84*4882a593Smuzhiyun			label = "user:sw4";
85*4882a593Smuzhiyun			linux,code = <KEY_F2>;
86*4882a593Smuzhiyun			gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>;
87*4882a593Smuzhiyun		};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun		button7 {
90*4882a593Smuzhiyun			label = "user:sw5";
91*4882a593Smuzhiyun			linux,code = <KEY_F3>;
92*4882a593Smuzhiyun			gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>;
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	pca_leds {
97*4882a593Smuzhiyun		compatible = "gpio-leds";
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun		led0 {
100*4882a593Smuzhiyun			label = "ext:led0";
101*4882a593Smuzhiyun			gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>;
102*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
103*4882a593Smuzhiyun		};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun		led1 {
106*4882a593Smuzhiyun			label = "ext:led1";
107*4882a593Smuzhiyun			gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>;
108*4882a593Smuzhiyun		};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun		led2 {
111*4882a593Smuzhiyun			label = "ext:led2";
112*4882a593Smuzhiyun			gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>;
113*4882a593Smuzhiyun		};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun		led3 {
116*4882a593Smuzhiyun			label = "ext:led3";
117*4882a593Smuzhiyun			gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>;
118*4882a593Smuzhiyun		};
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	vcc: vcc_fixed {
122*4882a593Smuzhiyun		compatible = "regulator-fixed";
123*4882a593Smuzhiyun		regulator-name = "3v3io";
124*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
125*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun&pinctrl {
130*4882a593Smuzhiyun	adc1_pins: adc1-pins {
131*4882a593Smuzhiyun		adc1_pins_cfg {
132*4882a593Smuzhiyun			pins = "pf_9";
133*4882a593Smuzhiyun			function = "adc";
134*4882a593Smuzhiyun			input-disable;
135*4882a593Smuzhiyun			bias-disable;
136*4882a593Smuzhiyun		};
137*4882a593Smuzhiyun	};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun	emc_pins: emc-pins {
140*4882a593Smuzhiyun		emc_addr0_23_cfg {
141*4882a593Smuzhiyun			pins =	"p2_9",  "p2_10", "p2_11", "p2_12",
142*4882a593Smuzhiyun				"p2_13", "p1_0",  "p1_1",  "p1_2",
143*4882a593Smuzhiyun				"p2_8",  "p2_7",  "p2_6",  "p2_2",
144*4882a593Smuzhiyun				"p2_1",  "p2_0",  "p6_8",  "p6_7",
145*4882a593Smuzhiyun				"pd_16", "pd_15", "pe_0",  "pe_1",
146*4882a593Smuzhiyun				"pe_2",  "pe_3",  "pe_4",  "pa_4";
147*4882a593Smuzhiyun			function = "emc";
148*4882a593Smuzhiyun			slew-rate = <1>;
149*4882a593Smuzhiyun			bias-disable;
150*4882a593Smuzhiyun			input-enable;
151*4882a593Smuzhiyun			input-schmitt-disable;
152*4882a593Smuzhiyun		};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun		emc_data0_15_cfg {
155*4882a593Smuzhiyun			pins =	"p1_7",  "p1_8",  "p1_9",  "p1_10",
156*4882a593Smuzhiyun				"p1_11", "p1_12", "p1_13", "p1_14",
157*4882a593Smuzhiyun				"p5_4",  "p5_5",  "p5_6",  "p5_7",
158*4882a593Smuzhiyun				"p5_0",  "p5_1",  "p5_2",  "p5_3";
159*4882a593Smuzhiyun			function = "emc";
160*4882a593Smuzhiyun			slew-rate = <1>;
161*4882a593Smuzhiyun			bias-disable;
162*4882a593Smuzhiyun			input-enable;
163*4882a593Smuzhiyun			input-schmitt-disable;
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun		emc_we_oe_cfg {
167*4882a593Smuzhiyun			pins = "p1_6", "p1_3";
168*4882a593Smuzhiyun			function = "emc";
169*4882a593Smuzhiyun			slew-rate = <1>;
170*4882a593Smuzhiyun			bias-disable;
171*4882a593Smuzhiyun			input-enable;
172*4882a593Smuzhiyun			input-schmitt-disable;
173*4882a593Smuzhiyun		};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun		emc_bls0_3_cfg {
176*4882a593Smuzhiyun			pins = "p1_4", "p6_6", "pd_13", "pd_10";
177*4882a593Smuzhiyun			function = "emc";
178*4882a593Smuzhiyun			slew-rate = <1>;
179*4882a593Smuzhiyun			bias-disable;
180*4882a593Smuzhiyun			input-enable;
181*4882a593Smuzhiyun			input-schmitt-disable;
182*4882a593Smuzhiyun		};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun		emc_cs0_cs2_cfg {
185*4882a593Smuzhiyun			pins = "p1_5", "pd_12";
186*4882a593Smuzhiyun			function = "emc";
187*4882a593Smuzhiyun			slew-rate = <1>;
188*4882a593Smuzhiyun			bias-disable;
189*4882a593Smuzhiyun			input-enable;
190*4882a593Smuzhiyun			input-schmitt-disable;
191*4882a593Smuzhiyun		};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun		emc_sdram_dqm0_3_cfg {
194*4882a593Smuzhiyun			pins = "p6_12", "p6_10", "pd_0", "pe_13";
195*4882a593Smuzhiyun			function = "emc";
196*4882a593Smuzhiyun			slew-rate = <1>;
197*4882a593Smuzhiyun			bias-disable;
198*4882a593Smuzhiyun			input-enable;
199*4882a593Smuzhiyun			input-schmitt-disable;
200*4882a593Smuzhiyun		};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun		emc_sdram_ras_cas_cfg {
203*4882a593Smuzhiyun			pins = "p6_5", "p6_4";
204*4882a593Smuzhiyun			function = "emc";
205*4882a593Smuzhiyun			slew-rate = <1>;
206*4882a593Smuzhiyun			bias-disable;
207*4882a593Smuzhiyun			input-enable;
208*4882a593Smuzhiyun			input-schmitt-disable;
209*4882a593Smuzhiyun		};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun		emc_sdram_dycs0_cfg {
212*4882a593Smuzhiyun			pins = "p6_9";
213*4882a593Smuzhiyun			function = "emc";
214*4882a593Smuzhiyun			slew-rate = <1>;
215*4882a593Smuzhiyun			bias-disable;
216*4882a593Smuzhiyun			input-enable;
217*4882a593Smuzhiyun			input-schmitt-disable;
218*4882a593Smuzhiyun		};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun		emc_sdram_cke_cfg {
221*4882a593Smuzhiyun			pins = "p6_11";
222*4882a593Smuzhiyun			function = "emc";
223*4882a593Smuzhiyun			slew-rate = <1>;
224*4882a593Smuzhiyun			bias-disable;
225*4882a593Smuzhiyun			input-enable;
226*4882a593Smuzhiyun			input-schmitt-disable;
227*4882a593Smuzhiyun		};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun		emc_sdram_clock_cfg {
230*4882a593Smuzhiyun			pins = "clk0", "clk1", "clk2", "clk3";
231*4882a593Smuzhiyun			function = "emc";
232*4882a593Smuzhiyun			slew-rate = <1>;
233*4882a593Smuzhiyun			bias-disable;
234*4882a593Smuzhiyun			input-enable;
235*4882a593Smuzhiyun			input-schmitt-disable;
236*4882a593Smuzhiyun		};
237*4882a593Smuzhiyun	};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun	enet_mii_pins: enet-mii-pins {
240*4882a593Smuzhiyun		enet_mii_rxd0_3_cfg {
241*4882a593Smuzhiyun			pins = "p1_15", "p0_0", "p9_3", "p9_2";
242*4882a593Smuzhiyun			function = "enet";
243*4882a593Smuzhiyun			bias-disable;
244*4882a593Smuzhiyun			input-enable;
245*4882a593Smuzhiyun		};
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun		enet_mii_txd0_3_cfg {
248*4882a593Smuzhiyun			pins = "p1_18", "p1_20", "p9_4", "p9_5";
249*4882a593Smuzhiyun			function = "enet";
250*4882a593Smuzhiyun			bias-disable;
251*4882a593Smuzhiyun		};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun		enet_mii_crs_col_cfg {
254*4882a593Smuzhiyun			pins = "p9_0", "p9_6";
255*4882a593Smuzhiyun			function = "enet";
256*4882a593Smuzhiyun			bias-disable;
257*4882a593Smuzhiyun			input-enable;
258*4882a593Smuzhiyun		};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun		enet_mii_rx_clk_dv_er_cfg {
261*4882a593Smuzhiyun			pins = "pc_0", "p1_16", "p9_1";
262*4882a593Smuzhiyun			function = "enet";
263*4882a593Smuzhiyun			bias-disable;
264*4882a593Smuzhiyun			input-enable;
265*4882a593Smuzhiyun		};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun		enet_mii_tx_clk_en_cfg {
268*4882a593Smuzhiyun			pins = "p1_19", "p0_1";
269*4882a593Smuzhiyun			function = "enet";
270*4882a593Smuzhiyun			bias-disable;
271*4882a593Smuzhiyun			input-enable;
272*4882a593Smuzhiyun		};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun		enet_mdio_cfg {
275*4882a593Smuzhiyun			pins = "p1_17";
276*4882a593Smuzhiyun			function = "enet";
277*4882a593Smuzhiyun			bias-disable;
278*4882a593Smuzhiyun			input-enable;
279*4882a593Smuzhiyun		};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun		enet_mdc_cfg {
282*4882a593Smuzhiyun			pins = "pc_1";
283*4882a593Smuzhiyun			function = "enet";
284*4882a593Smuzhiyun			bias-disable;
285*4882a593Smuzhiyun		};
286*4882a593Smuzhiyun	};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun	i2c0_pins: i2c0-pins {
289*4882a593Smuzhiyun		i2c0_pins_cfg {
290*4882a593Smuzhiyun			pins = "i2c0_scl", "i2c0_sda";
291*4882a593Smuzhiyun			function = "i2c0";
292*4882a593Smuzhiyun			input-enable;
293*4882a593Smuzhiyun		};
294*4882a593Smuzhiyun	};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	spifi_pins: spifi-pins {
297*4882a593Smuzhiyun		spifi_clk_cfg {
298*4882a593Smuzhiyun			pins = "p3_3";
299*4882a593Smuzhiyun			function = "spifi";
300*4882a593Smuzhiyun			slew-rate = <1>;
301*4882a593Smuzhiyun			bias-disable;
302*4882a593Smuzhiyun			input-enable;
303*4882a593Smuzhiyun			input-schmitt-disable;
304*4882a593Smuzhiyun		};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun		spifi_mosi_miso_sio2_3_cfg {
307*4882a593Smuzhiyun			pins = "p3_7", "p3_6", "p3_5", "p3_4";
308*4882a593Smuzhiyun			function = "spifi";
309*4882a593Smuzhiyun			slew-rate = <1>;
310*4882a593Smuzhiyun			bias-disable;
311*4882a593Smuzhiyun			input-enable;
312*4882a593Smuzhiyun			input-schmitt-disable;
313*4882a593Smuzhiyun		};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun		spifi_cs_cfg {
316*4882a593Smuzhiyun			pins = "p3_8";
317*4882a593Smuzhiyun			function = "spifi";
318*4882a593Smuzhiyun			slew-rate = <1>;
319*4882a593Smuzhiyun			bias-disable;
320*4882a593Smuzhiyun			input-enable;
321*4882a593Smuzhiyun			input-schmitt-disable;
322*4882a593Smuzhiyun		};
323*4882a593Smuzhiyun	};
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun	uart0_pins: uart0-pins {
326*4882a593Smuzhiyun		uart0_rx_cfg {
327*4882a593Smuzhiyun			pins = "pf_11";
328*4882a593Smuzhiyun			function = "uart0";
329*4882a593Smuzhiyun			input-schmitt-disable;
330*4882a593Smuzhiyun			bias-disable;
331*4882a593Smuzhiyun			input-enable;
332*4882a593Smuzhiyun		};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun		uart0_tx_cfg {
335*4882a593Smuzhiyun			pins = "pf_10";
336*4882a593Smuzhiyun			function = "uart0";
337*4882a593Smuzhiyun			bias-pull-down;
338*4882a593Smuzhiyun		};
339*4882a593Smuzhiyun	};
340*4882a593Smuzhiyun};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun&adc1 {
343*4882a593Smuzhiyun	status = "okay";
344*4882a593Smuzhiyun	vref-supply = <&vcc>;
345*4882a593Smuzhiyun	pinctrl-names = "default";
346*4882a593Smuzhiyun	pinctrl-0 = <&adc1_pins>;
347*4882a593Smuzhiyun};
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun&emc {
350*4882a593Smuzhiyun	status = "okay";
351*4882a593Smuzhiyun	pinctrl-names = "default";
352*4882a593Smuzhiyun	pinctrl-0 = <&emc_pins>;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun	cs0 {
355*4882a593Smuzhiyun		#address-cells = <2>;
356*4882a593Smuzhiyun		#size-cells = <1>;
357*4882a593Smuzhiyun		ranges;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun		mpmc,cs = <0>;
360*4882a593Smuzhiyun		mpmc,memory-width = <16>;
361*4882a593Smuzhiyun		mpmc,byte-lane-low;
362*4882a593Smuzhiyun		mpmc,write-enable-delay = <0>;
363*4882a593Smuzhiyun		mpmc,output-enable-delay = <0>;
364*4882a593Smuzhiyun		mpmc,read-access-delay = <70>;
365*4882a593Smuzhiyun		mpmc,page-mode-read-delay = <70>;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun		flash@0,0 {
368*4882a593Smuzhiyun			compatible = "sst,sst39vf320", "cfi-flash";
369*4882a593Smuzhiyun			reg = <0 0 0x400000>;
370*4882a593Smuzhiyun			bank-width = <2>;
371*4882a593Smuzhiyun			#address-cells = <1>;
372*4882a593Smuzhiyun			#size-cells = <1>;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun			partition@0 {
375*4882a593Smuzhiyun				label = "bootloader";
376*4882a593Smuzhiyun				reg = <0x000000 0x040000>; /* 256 KiB */
377*4882a593Smuzhiyun			};
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun			partition@1 {
380*4882a593Smuzhiyun				label = "kernel";
381*4882a593Smuzhiyun				reg = <0x040000 0x2C0000>; /* 2.75 MiB */
382*4882a593Smuzhiyun			};
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun			partition@2 {
385*4882a593Smuzhiyun				label = "rootfs";
386*4882a593Smuzhiyun				reg = <0x300000 0x100000>; /* 1 MiB */
387*4882a593Smuzhiyun			};
388*4882a593Smuzhiyun		};
389*4882a593Smuzhiyun	};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun	cs2 {
392*4882a593Smuzhiyun		#address-cells = <2>;
393*4882a593Smuzhiyun		#size-cells = <1>;
394*4882a593Smuzhiyun		ranges;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun		mpmc,cs = <2>;
397*4882a593Smuzhiyun		mpmc,memory-width = <16>;
398*4882a593Smuzhiyun		mpmc,byte-lane-low;
399*4882a593Smuzhiyun		mpmc,write-enable-delay = <0>;
400*4882a593Smuzhiyun		mpmc,output-enable-delay = <30>;
401*4882a593Smuzhiyun		mpmc,read-access-delay = <90>;
402*4882a593Smuzhiyun		mpmc,page-mode-read-delay = <55>;
403*4882a593Smuzhiyun		mpmc,write-access-delay = <55>;
404*4882a593Smuzhiyun		mpmc,turn-round-delay = <55>;
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun		ext_sram: sram@2,0 {
407*4882a593Smuzhiyun			compatible = "mmio-sram";
408*4882a593Smuzhiyun			reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */
409*4882a593Smuzhiyun		};
410*4882a593Smuzhiyun	};
411*4882a593Smuzhiyun};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun&enet_tx_clk {
414*4882a593Smuzhiyun	clock-frequency = <25000000>;
415*4882a593Smuzhiyun};
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun&i2c0 {
418*4882a593Smuzhiyun	status = "okay";
419*4882a593Smuzhiyun	pinctrl-names = "default";
420*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
421*4882a593Smuzhiyun	clock-frequency = <400000>;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun	/* NXP SE97BTP with temperature sensor + eeprom */
424*4882a593Smuzhiyun	sensor@18 {
425*4882a593Smuzhiyun		compatible = "nxp,se97", "jedec,jc-42.4-temp";
426*4882a593Smuzhiyun		reg = <0x18>;
427*4882a593Smuzhiyun	};
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun	eeprom@50 {
430*4882a593Smuzhiyun		compatible = "nxp,24c02", "atmel,24c02";
431*4882a593Smuzhiyun		reg = <0x50>;
432*4882a593Smuzhiyun	};
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun	pca_gpio: gpio@24 {
435*4882a593Smuzhiyun		compatible = "nxp,pca9673";
436*4882a593Smuzhiyun		reg = <0x24>;
437*4882a593Smuzhiyun		gpio-controller;
438*4882a593Smuzhiyun		#gpio-cells = <2>;
439*4882a593Smuzhiyun	};
440*4882a593Smuzhiyun};
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun&mac {
443*4882a593Smuzhiyun	status = "okay";
444*4882a593Smuzhiyun	phy-mode = "mii";
445*4882a593Smuzhiyun	pinctrl-names = "default";
446*4882a593Smuzhiyun	pinctrl-0 = <&enet_mii_pins>;
447*4882a593Smuzhiyun};
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun&spifi {
450*4882a593Smuzhiyun	status = "okay";
451*4882a593Smuzhiyun	pinctrl-names = "default";
452*4882a593Smuzhiyun	pinctrl-0 = <&spifi_pins>;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun	flash {
455*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
456*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
457*4882a593Smuzhiyun		#address-cells = <1>;
458*4882a593Smuzhiyun		#size-cells = <1>;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun		partition@0 {
461*4882a593Smuzhiyun			label = "bootloader";
462*4882a593Smuzhiyun			reg = <0x000000 0x040000>; /* 256 KiB */
463*4882a593Smuzhiyun		};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun		partition@1 {
466*4882a593Smuzhiyun			label = "kernel";
467*4882a593Smuzhiyun			reg = <0x040000 0x2c0000>; /* 2.75 MiB */
468*4882a593Smuzhiyun		};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun		partition@2 {
471*4882a593Smuzhiyun			label = "rootfs";
472*4882a593Smuzhiyun			reg = <0x300000 0x500000>; /* 5 MiB */
473*4882a593Smuzhiyun		};
474*4882a593Smuzhiyun	};
475*4882a593Smuzhiyun};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun&uart0 {
478*4882a593Smuzhiyun	status = "okay";
479*4882a593Smuzhiyun	pinctrl-names = "default";
480*4882a593Smuzhiyun	pinctrl-0 = <&uart0_pins>;
481*4882a593Smuzhiyun};
482