1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 4*4882a593Smuzhiyun * inspired by the board files made by Kevin Mihelich for ArchLinux, 5*4882a593Smuzhiyun * and their DTS file. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2015 Linus Walleij <linus.walleij@linaro.org> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/dts-v1/; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include "kirkwood.dtsi" 13*4882a593Smuzhiyun#include "kirkwood-6192.dtsi" 14*4882a593Smuzhiyun#include <dt-bindings/input/linux-event-codes.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun model = "Cloud Engines PogoPlug Series 4"; 18*4882a593Smuzhiyun compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", 19*4882a593Smuzhiyun "marvell,kirkwood"; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory { 22*4882a593Smuzhiyun device_type = "memory"; 23*4882a593Smuzhiyun reg = <0x00000000 0x08000000>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun chosen { 27*4882a593Smuzhiyun stdout-path = "uart0:115200n8"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun gpio_keys { 31*4882a593Smuzhiyun compatible = "gpio-keys"; 32*4882a593Smuzhiyun #address-cells = <1>; 33*4882a593Smuzhiyun #size-cells = <0>; 34*4882a593Smuzhiyun pinctrl-0 = <&pmx_button_eject>; 35*4882a593Smuzhiyun pinctrl-names = "default"; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun eject { 38*4882a593Smuzhiyun debounce-interval = <50>; 39*4882a593Smuzhiyun wakeup-source; 40*4882a593Smuzhiyun linux,code = <KEY_EJECTCD>; 41*4882a593Smuzhiyun label = "Eject Button"; 42*4882a593Smuzhiyun gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun gpio-leds { 47*4882a593Smuzhiyun compatible = "gpio-leds"; 48*4882a593Smuzhiyun pinctrl-0 = <&pmx_led_green &pmx_led_red>; 49*4882a593Smuzhiyun pinctrl-names = "default"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun health { 52*4882a593Smuzhiyun label = "pogoplugv4:green:health"; 53*4882a593Smuzhiyun gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; 54*4882a593Smuzhiyun default-state = "on"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun fault { 57*4882a593Smuzhiyun label = "pogoplugv4:red:fault"; 58*4882a593Smuzhiyun gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun&pinctrl { 64*4882a593Smuzhiyun pmx_sata0: pmx-sata0 { 65*4882a593Smuzhiyun marvell,pins = "mpp21"; 66*4882a593Smuzhiyun marvell,function = "sata0"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun pmx_sata1: pmx-sata1 { 70*4882a593Smuzhiyun marvell,pins = "mpp20"; 71*4882a593Smuzhiyun marvell,function = "sata1"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun pmx_sdio_cd: pmx-sdio-cd { 75*4882a593Smuzhiyun marvell,pins = "mpp27"; 76*4882a593Smuzhiyun marvell,function = "gpio"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun pmx_sdio_wp: pmx-sdio-wp { 80*4882a593Smuzhiyun marvell,pins = "mpp28"; 81*4882a593Smuzhiyun marvell,function = "gpio"; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun pmx_button_eject: pmx-button-eject { 85*4882a593Smuzhiyun marvell,pins = "mpp29"; 86*4882a593Smuzhiyun marvell,function = "gpio"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun pmx_led_green: pmx-led-green { 90*4882a593Smuzhiyun marvell,pins = "mpp22"; 91*4882a593Smuzhiyun marvell,function = "gpio"; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun pmx_led_red: pmx-led-red { 95*4882a593Smuzhiyun marvell,pins = "mpp24"; 96*4882a593Smuzhiyun marvell,function = "gpio"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&uart0 { 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun/* 105*4882a593Smuzhiyun * This PCIE controller has a USB 3.0 XHCI controller at 1,0 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun&pciec { 108*4882a593Smuzhiyun status = "okay"; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&pcie0 { 112*4882a593Smuzhiyun status = "okay"; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun&sata { 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun pinctrl-0 = <&pmx_sata0 &pmx_sata1>; 118*4882a593Smuzhiyun pinctrl-names = "default"; 119*4882a593Smuzhiyun nr-ports = <1>; 120*4882a593Smuzhiyun}; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun&sdio { 123*4882a593Smuzhiyun status = "okay"; 124*4882a593Smuzhiyun pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; 125*4882a593Smuzhiyun pinctrl-names = "default"; 126*4882a593Smuzhiyun cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; 127*4882a593Smuzhiyun wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&nand { 131*4882a593Smuzhiyun /* 128 MiB of NAND flash */ 132*4882a593Smuzhiyun chip-delay = <40>; 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun partitions { 135*4882a593Smuzhiyun compatible = "fixed-partitions"; 136*4882a593Smuzhiyun #address-cells = <1>; 137*4882a593Smuzhiyun #size-cells = <1>; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun partition@0 { 140*4882a593Smuzhiyun label = "u-boot"; 141*4882a593Smuzhiyun reg = <0x00000000 0x200000>; 142*4882a593Smuzhiyun read-only; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun partition@200000 { 146*4882a593Smuzhiyun label = "uImage"; 147*4882a593Smuzhiyun reg = <0x00200000 0x300000>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun partition@500000 { 151*4882a593Smuzhiyun label = "uImage2"; 152*4882a593Smuzhiyun reg = <0x00500000 0x300000>; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun partition@800000 { 156*4882a593Smuzhiyun label = "failsafe"; 157*4882a593Smuzhiyun reg = <0x00800000 0x800000>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun partition@1000000 { 161*4882a593Smuzhiyun label = "root"; 162*4882a593Smuzhiyun reg = <0x01000000 0x7000000>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun}; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun&mdio { 168*4882a593Smuzhiyun status = "okay"; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 171*4882a593Smuzhiyun reg = <0>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyunð0 { 176*4882a593Smuzhiyun status = "okay"; 177*4882a593Smuzhiyun ethernet0-port@0 { 178*4882a593Smuzhiyun phy-handle = <ðphy0>; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun}; 181