xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/kirkwood-linksys-viper.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (c) 2013 Jonas Gorski <jogo@openwrt.org>
6*4882a593Smuzhiyun * (c) 2013 Deutsche Telekom Innovation Laboratories
7*4882a593Smuzhiyun * (c) 2014 Luka Perkov <luka@openwrt.org>
8*4882a593Smuzhiyun * (c) 2014 Randy C. Will <randall.will@gmail.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/dts-v1/;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun#include "kirkwood.dtsi"
15*4882a593Smuzhiyun#include "kirkwood-6282.dtsi"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun/ {
18*4882a593Smuzhiyun	model = "Linksys Viper (E4200v2 / EA4500)";
19*4882a593Smuzhiyun	compatible = "linksys,viper", "marvell,kirkwood-88f6282", "marvell,kirkwood";
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	memory {
22*4882a593Smuzhiyun		device_type = "memory";
23*4882a593Smuzhiyun		reg = <0x00000000 0x8000000>;
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	aliases {
27*4882a593Smuzhiyun		serial0 = &uart0;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	chosen {
31*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	gpio_keys {
35*4882a593Smuzhiyun		compatible = "gpio-keys";
36*4882a593Smuzhiyun		#address-cells = <1>;
37*4882a593Smuzhiyun		#size-cells = <0>;
38*4882a593Smuzhiyun		pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >;
39*4882a593Smuzhiyun		pinctrl-names = "default";
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun		wps {
42*4882a593Smuzhiyun			label = "WPS Button";
43*4882a593Smuzhiyun			linux,code = <KEY_WPS_BUTTON>;
44*4882a593Smuzhiyun			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun		reset {
48*4882a593Smuzhiyun			label = "Reset Button";
49*4882a593Smuzhiyun			linux,code = <KEY_RESTART>;
50*4882a593Smuzhiyun			gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	gpio-leds {
55*4882a593Smuzhiyun		compatible = "gpio-leds";
56*4882a593Smuzhiyun		pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >;
57*4882a593Smuzhiyun		pinctrl-names = "default";
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun		white-health {
60*4882a593Smuzhiyun			label = "viper:white:health";
61*4882a593Smuzhiyun			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
62*4882a593Smuzhiyun		};
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun		white-pulse {
65*4882a593Smuzhiyun			label = "viper:white:pulse";
66*4882a593Smuzhiyun			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun&pinctrl {
72*4882a593Smuzhiyun	pmx_led_white_health: pmx-led-white-health {
73*4882a593Smuzhiyun		marvell,pins = "mpp7";
74*4882a593Smuzhiyun		marvell,function = "gpo";
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun	pmx_led_white_pulse: pmx-led-white-pulse {
77*4882a593Smuzhiyun		marvell,pins = "mpp14";
78*4882a593Smuzhiyun		marvell,function = "gpio";
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun	pmx_btn_wps: pmx-btn-wps {
81*4882a593Smuzhiyun		marvell,pins = "mpp47";
82*4882a593Smuzhiyun		marvell,function = "gpio";
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun	pmx_btn_reset: pmx-btn-reset {
85*4882a593Smuzhiyun		marvell,pins = "mpp48";
86*4882a593Smuzhiyun		marvell,function = "gpio";
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&nand {
91*4882a593Smuzhiyun	status = "okay";
92*4882a593Smuzhiyun	pinctrl-0 = <&pmx_nand>;
93*4882a593Smuzhiyun	pinctrl-names = "default";
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun	partitions {
96*4882a593Smuzhiyun		compatible = "fixed-partitions";
97*4882a593Smuzhiyun		#address-cells = <1>;
98*4882a593Smuzhiyun		#size-cells = <1>;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun		partition@0 {
101*4882a593Smuzhiyun			label = "u-boot";
102*4882a593Smuzhiyun			reg = <0x0 0x80000>;
103*4882a593Smuzhiyun			read-only;
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun		partition@80000 {
107*4882a593Smuzhiyun			label = "u_env";
108*4882a593Smuzhiyun			reg = <0x80000 0x20000>;
109*4882a593Smuzhiyun		};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun		partition@a0000 {
112*4882a593Smuzhiyun			label = "s_env";
113*4882a593Smuzhiyun			reg = <0xA0000 0x20000>;
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun		partition@200000 {
117*4882a593Smuzhiyun			label = "kernel";
118*4882a593Smuzhiyun			reg = <0x200000 0x2A0000>;
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		partition@4a0000 {
122*4882a593Smuzhiyun			label = "rootfs";
123*4882a593Smuzhiyun			reg = <0x4A0000 0x1760000>;
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun		partition@1c00000 {
127*4882a593Smuzhiyun			label = "alt_kernel";
128*4882a593Smuzhiyun			reg = <0x1C00000 0x2A0000>;
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun		partition@1ea0000 {
132*4882a593Smuzhiyun			label = "alt_rootfs";
133*4882a593Smuzhiyun			reg = <0x1EA0000 0x1760000>;
134*4882a593Smuzhiyun		};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun		partition@3600000 {
137*4882a593Smuzhiyun			label = "syscfg";
138*4882a593Smuzhiyun			reg = <0x3600000 0x4A00000>;
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		partition@c0000 {
142*4882a593Smuzhiyun			label = "unused";
143*4882a593Smuzhiyun			reg = <0xC0000 0x140000>;
144*4882a593Smuzhiyun		};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun	};
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&pciec {
150*4882a593Smuzhiyun	status = "okay";
151*4882a593Smuzhiyun};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun&pcie0 {
154*4882a593Smuzhiyun	status = "okay";
155*4882a593Smuzhiyun};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun&pcie1 {
158*4882a593Smuzhiyun	status = "okay";
159*4882a593Smuzhiyun};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun&mdio {
162*4882a593Smuzhiyun	status = "okay";
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun	switch@10 {
165*4882a593Smuzhiyun		compatible = "marvell,mv88e6085";
166*4882a593Smuzhiyun		#address-cells = <1>;
167*4882a593Smuzhiyun		#size-cells = <0>;
168*4882a593Smuzhiyun		reg = <16>;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun		ports {
171*4882a593Smuzhiyun			#address-cells = <1>;
172*4882a593Smuzhiyun			#size-cells = <0>;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun			port@0 {
175*4882a593Smuzhiyun				reg = <0>;
176*4882a593Smuzhiyun				label = "ethernet1";
177*4882a593Smuzhiyun			};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun			port@1 {
180*4882a593Smuzhiyun				reg = <1>;
181*4882a593Smuzhiyun				label = "ethernet2";
182*4882a593Smuzhiyun			};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun			port@2 {
185*4882a593Smuzhiyun				reg = <2>;
186*4882a593Smuzhiyun				label = "ethernet3";
187*4882a593Smuzhiyun			};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun			port@3 {
190*4882a593Smuzhiyun				reg = <3>;
191*4882a593Smuzhiyun				label = "ethernet4";
192*4882a593Smuzhiyun			};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun			port@4 {
195*4882a593Smuzhiyun				reg = <4>;
196*4882a593Smuzhiyun				label = "internet";
197*4882a593Smuzhiyun			};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun			port@5 {
200*4882a593Smuzhiyun				reg = <5>;
201*4882a593Smuzhiyun				label = "cpu";
202*4882a593Smuzhiyun				ethernet = <&eth0port>;
203*4882a593Smuzhiyun				fixed-link {
204*4882a593Smuzhiyun					speed = <1000>;
205*4882a593Smuzhiyun					full-duplex;
206*4882a593Smuzhiyun				};
207*4882a593Smuzhiyun			};
208*4882a593Smuzhiyun		};
209*4882a593Smuzhiyun	};
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&uart0 {
213*4882a593Smuzhiyun	status = "okay";
214*4882a593Smuzhiyun};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set
217*4882a593Smuzhiyun * fixed speed and duplex.
218*4882a593Smuzhiyun */
219*4882a593Smuzhiyun&eth0 {
220*4882a593Smuzhiyun	status = "okay";
221*4882a593Smuzhiyun	ethernet0-port@0 {
222*4882a593Smuzhiyun		speed = <1000>;
223*4882a593Smuzhiyun		duplex = <1>;
224*4882a593Smuzhiyun	};
225*4882a593Smuzhiyun};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun/* eth1 is connected to the switch at port 6. However DSA only supports a
228*4882a593Smuzhiyun * single CPU port. So leave this port disabled to avoid confusion.
229*4882a593Smuzhiyun */
230*4882a593Smuzhiyun&eth1 {
231*4882a593Smuzhiyun	status = "disabled";
232*4882a593Smuzhiyun};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun/* There is no battery on the board, so the RTC does not keep
235*4882a593Smuzhiyun * time when there is no power, making it useless.
236*4882a593Smuzhiyun */
237*4882a593Smuzhiyun&rtc {
238*4882a593Smuzhiyun	status = "disabled";
239*4882a593Smuzhiyun};
240*4882a593Smuzhiyun
241