xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/kirkwood-l-50.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Check Point L-50 Board Description
4*4882a593Smuzhiyun * Copyright 2020 Pawel Dembicki <paweldembicki@gmail.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "kirkwood.dtsi"
10*4882a593Smuzhiyun#include "kirkwood-6281.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Check Point L-50";
14*4882a593Smuzhiyun	compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	memory {
17*4882a593Smuzhiyun		device_type = "memory";
18*4882a593Smuzhiyun		reg = <0x00000000 0x20000000>;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	chosen {
22*4882a593Smuzhiyun		bootargs = "console=ttyS0,115200n8";
23*4882a593Smuzhiyun		stdout-path = &uart0;
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	ocp@f1000000 {
27*4882a593Smuzhiyun		pinctrl: pin-controller@10000 {
28*4882a593Smuzhiyun			pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
29*4882a593Smuzhiyun			pinctrl-names = "default";
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun			pmx_sysrst: pmx-sysrst {
32*4882a593Smuzhiyun				marvell,pins = "mpp6";
33*4882a593Smuzhiyun				marvell,function = "sysrst";
34*4882a593Smuzhiyun			};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun			pmx_button29: pmx_button29 {
37*4882a593Smuzhiyun				marvell,pins = "mpp29";
38*4882a593Smuzhiyun				marvell,function = "gpio";
39*4882a593Smuzhiyun			};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun			pmx_led38: pmx_led38 {
42*4882a593Smuzhiyun				marvell,pins = "mpp38";
43*4882a593Smuzhiyun				marvell,function = "gpio";
44*4882a593Smuzhiyun			};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun			pmx_sdio_cd: pmx-sdio-cd {
47*4882a593Smuzhiyun				marvell,pins = "mpp46";
48*4882a593Smuzhiyun				marvell,function = "gpio";
49*4882a593Smuzhiyun			};
50*4882a593Smuzhiyun		};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun		serial@12000 {
53*4882a593Smuzhiyun			status = "okay";
54*4882a593Smuzhiyun		};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun		mvsdio@90000 {
57*4882a593Smuzhiyun			status = "okay";
58*4882a593Smuzhiyun			cd-gpios = <&gpio1 14 9>;
59*4882a593Smuzhiyun		};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun		i2c@11000 {
62*4882a593Smuzhiyun			status = "okay";
63*4882a593Smuzhiyun			clock-frequency = <400000>;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun			gpio2: gpio-expander@20{
66*4882a593Smuzhiyun				#gpio-cells = <2>;
67*4882a593Smuzhiyun				#interrupt-cells = <2>;
68*4882a593Smuzhiyun				compatible = "semtech,sx1505q";
69*4882a593Smuzhiyun				reg = <0x20>;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun				gpio-controller;
72*4882a593Smuzhiyun			};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun			/* Three GPIOs from 0x21 exp. are undescribed in dts:
75*4882a593Smuzhiyun			 * 1: DSL module reset (active low)
76*4882a593Smuzhiyun			 * 5: mPCIE reset (active low)
77*4882a593Smuzhiyun			 * 6: Express card reset (active low)
78*4882a593Smuzhiyun			 */
79*4882a593Smuzhiyun			gpio3: gpio-expander@21{
80*4882a593Smuzhiyun				#gpio-cells = <2>;
81*4882a593Smuzhiyun				#interrupt-cells = <2>;
82*4882a593Smuzhiyun				compatible = "semtech,sx1505q";
83*4882a593Smuzhiyun				reg = <0x21>;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun				gpio-controller;
86*4882a593Smuzhiyun			};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun			rtc@30 {
89*4882a593Smuzhiyun				compatible = "s35390a";
90*4882a593Smuzhiyun				reg = <0x30>;
91*4882a593Smuzhiyun			};
92*4882a593Smuzhiyun		};
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun	leds {
96*4882a593Smuzhiyun		compatible = "gpio-leds";
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun		status_green {
99*4882a593Smuzhiyun			label = "l-50:green:status";
100*4882a593Smuzhiyun			gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
101*4882a593Smuzhiyun		};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun		status_red {
104*4882a593Smuzhiyun			label = "l-50:red:status";
105*4882a593Smuzhiyun			gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
106*4882a593Smuzhiyun		};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun		wifi {
109*4882a593Smuzhiyun			label = "l-50:green:wifi";
110*4882a593Smuzhiyun			gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
111*4882a593Smuzhiyun			linux,default-trigger = "phy0tpt";
112*4882a593Smuzhiyun		};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun		internet_green {
115*4882a593Smuzhiyun			label = "l-50:green:internet";
116*4882a593Smuzhiyun			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
117*4882a593Smuzhiyun		};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun		internet_red {
120*4882a593Smuzhiyun			label = "l-50:red:internet";
121*4882a593Smuzhiyun			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
122*4882a593Smuzhiyun		};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun		usb1_green {
125*4882a593Smuzhiyun			label = "l-50:green:usb1";
126*4882a593Smuzhiyun			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
127*4882a593Smuzhiyun			linux,default-trigger = "usbport";
128*4882a593Smuzhiyun			trigger-sources = <&hub_port3>;
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun		usb1_red {
132*4882a593Smuzhiyun			label = "l-50:red:usb1";
133*4882a593Smuzhiyun			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
134*4882a593Smuzhiyun		};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun		usb2_green {
137*4882a593Smuzhiyun			label = "l-50:green:usb2";
138*4882a593Smuzhiyun			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
139*4882a593Smuzhiyun			linux,default-trigger = "usbport";
140*4882a593Smuzhiyun			trigger-sources = <&hub_port1>;
141*4882a593Smuzhiyun		};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun		usb2_red {
144*4882a593Smuzhiyun			label = "l-50:red:usb2";
145*4882a593Smuzhiyun			gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
146*4882a593Smuzhiyun		};
147*4882a593Smuzhiyun	};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun	usb2_pwr {
150*4882a593Smuzhiyun		compatible = "regulator-fixed";
151*4882a593Smuzhiyun		regulator-name = "usb2_pwr";
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
154*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
155*4882a593Smuzhiyun		gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
156*4882a593Smuzhiyun		regulator-always-on;
157*4882a593Smuzhiyun	};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun	usb1_pwr {
160*4882a593Smuzhiyun		compatible = "regulator-fixed";
161*4882a593Smuzhiyun		regulator-name = "usb1_pwr";
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
164*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
165*4882a593Smuzhiyun		gpio = <&gpio3 4 GPIO_ACTIVE_LOW>;
166*4882a593Smuzhiyun		regulator-always-on;
167*4882a593Smuzhiyun	};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun	mpcie_pwr {
170*4882a593Smuzhiyun		compatible = "regulator-fixed";
171*4882a593Smuzhiyun		regulator-name = "mpcie_pwr";
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
174*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
175*4882a593Smuzhiyun		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
176*4882a593Smuzhiyun		enable-active-high;
177*4882a593Smuzhiyun		regulator-always-on;
178*4882a593Smuzhiyun	};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun	express_card_pwr {
181*4882a593Smuzhiyun		compatible = "regulator-fixed";
182*4882a593Smuzhiyun		regulator-name = "express_card_pwr";
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
185*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
186*4882a593Smuzhiyun		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
187*4882a593Smuzhiyun		enable-active-high;
188*4882a593Smuzhiyun		regulator-always-on;
189*4882a593Smuzhiyun	};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun	keys {
192*4882a593Smuzhiyun		compatible = "gpio-keys";
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun		factory_defaults {
195*4882a593Smuzhiyun			label = "factory_defaults";
196*4882a593Smuzhiyun			gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
197*4882a593Smuzhiyun			linux,code = <KEY_RESTART>;
198*4882a593Smuzhiyun		};
199*4882a593Smuzhiyun	};
200*4882a593Smuzhiyun};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun&mdio {
203*4882a593Smuzhiyun	status = "okay";
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun	ethphy8: ethernet-phy@8 {
206*4882a593Smuzhiyun		reg = <0x08>;
207*4882a593Smuzhiyun	};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun	switch0: switch@10 {
210*4882a593Smuzhiyun		compatible = "marvell,mv88e6085";
211*4882a593Smuzhiyun		#address-cells = <1>;
212*4882a593Smuzhiyun		#size-cells = <0>;
213*4882a593Smuzhiyun		reg = <0x10>;
214*4882a593Smuzhiyun		dsa,member = <0 0>;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun		ports {
217*4882a593Smuzhiyun			#address-cells = <1>;
218*4882a593Smuzhiyun			#size-cells = <0>;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun			port@0 {
221*4882a593Smuzhiyun				reg = <0>;
222*4882a593Smuzhiyun				label = "lan5";
223*4882a593Smuzhiyun			};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun			port@1 {
226*4882a593Smuzhiyun			       reg = <1>;
227*4882a593Smuzhiyun			       label = "lan1";
228*4882a593Smuzhiyun			};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun			port@2 {
231*4882a593Smuzhiyun			       reg = <2>;
232*4882a593Smuzhiyun			       label = "lan6";
233*4882a593Smuzhiyun			};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun			port@3 {
236*4882a593Smuzhiyun			       reg = <3>;
237*4882a593Smuzhiyun			       label = "lan2";
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun			port@4 {
241*4882a593Smuzhiyun				reg = <4>;
242*4882a593Smuzhiyun				label = "lan7";
243*4882a593Smuzhiyun			};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun			switch0port5: port@5 {
246*4882a593Smuzhiyun				reg = <5>;
247*4882a593Smuzhiyun				phy-mode = "rgmii-txid";
248*4882a593Smuzhiyun				link = <&switch1port5>;
249*4882a593Smuzhiyun				fixed-link {
250*4882a593Smuzhiyun					speed = <1000>;
251*4882a593Smuzhiyun					full-duplex;
252*4882a593Smuzhiyun				};
253*4882a593Smuzhiyun			};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun			port@6 {
256*4882a593Smuzhiyun				reg = <6>;
257*4882a593Smuzhiyun				label = "cpu";
258*4882a593Smuzhiyun				phy-mode = "rgmii-id";
259*4882a593Smuzhiyun				ethernet = <&eth1port>;
260*4882a593Smuzhiyun				fixed-link {
261*4882a593Smuzhiyun					speed = <1000>;
262*4882a593Smuzhiyun					full-duplex;
263*4882a593Smuzhiyun				};
264*4882a593Smuzhiyun			};
265*4882a593Smuzhiyun		};
266*4882a593Smuzhiyun	};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun	switch@11 {
269*4882a593Smuzhiyun		compatible = "marvell,mv88e6085";
270*4882a593Smuzhiyun		#address-cells = <1>;
271*4882a593Smuzhiyun		#size-cells = <0>;
272*4882a593Smuzhiyun		reg = <0x11>;
273*4882a593Smuzhiyun		dsa,member = <0 1>;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun		ports {
276*4882a593Smuzhiyun			#address-cells = <1>;
277*4882a593Smuzhiyun			#size-cells = <0>;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun			port@0 {
280*4882a593Smuzhiyun				reg = <0>;
281*4882a593Smuzhiyun				label = "lan3";
282*4882a593Smuzhiyun			};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun			port@1 {
285*4882a593Smuzhiyun			       reg = <1>;
286*4882a593Smuzhiyun			       label = "lan8";
287*4882a593Smuzhiyun			};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun			port@2 {
290*4882a593Smuzhiyun			       reg = <2>;
291*4882a593Smuzhiyun			       label = "lan4";
292*4882a593Smuzhiyun			};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun			port@3 {
295*4882a593Smuzhiyun			       reg = <3>;
296*4882a593Smuzhiyun			       label = "dmz";
297*4882a593Smuzhiyun			};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun			switch1port5: port@5 {
300*4882a593Smuzhiyun				reg = <5>;
301*4882a593Smuzhiyun				phy-mode = "rgmii-txid";
302*4882a593Smuzhiyun				link = <&switch0port5>;
303*4882a593Smuzhiyun				fixed-link {
304*4882a593Smuzhiyun					speed = <1000>;
305*4882a593Smuzhiyun					full-duplex;
306*4882a593Smuzhiyun				};
307*4882a593Smuzhiyun			};
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun			port@6 {
310*4882a593Smuzhiyun				reg = <6>;
311*4882a593Smuzhiyun				label = "dsl";
312*4882a593Smuzhiyun				fixed-link {
313*4882a593Smuzhiyun					speed = <100>;
314*4882a593Smuzhiyun					full-duplex;
315*4882a593Smuzhiyun				};
316*4882a593Smuzhiyun			};
317*4882a593Smuzhiyun		};
318*4882a593Smuzhiyun	};
319*4882a593Smuzhiyun};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun&eth0 {
322*4882a593Smuzhiyun	status = "okay";
323*4882a593Smuzhiyun	ethernet0-port@0 {
324*4882a593Smuzhiyun		phy-handle = <&ethphy8>;
325*4882a593Smuzhiyun	};
326*4882a593Smuzhiyun};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun&eth1 {
329*4882a593Smuzhiyun	status = "okay";
330*4882a593Smuzhiyun	ethernet1-port@0 {
331*4882a593Smuzhiyun		speed = <1000>;
332*4882a593Smuzhiyun		duplex = <1>;
333*4882a593Smuzhiyun	};
334*4882a593Smuzhiyun};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun&nand {
337*4882a593Smuzhiyun	status = "okay";
338*4882a593Smuzhiyun	pinctrl-0 = <&pmx_nand>;
339*4882a593Smuzhiyun	pinctrl-names = "default";
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun	partition@0 {
342*4882a593Smuzhiyun		label = "u-boot";
343*4882a593Smuzhiyun		reg = <0x00000000 0x000c0000>;
344*4882a593Smuzhiyun	};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun	partition@a0000 {
347*4882a593Smuzhiyun		label = "bootldr-env";
348*4882a593Smuzhiyun		reg = <0x000c0000 0x00040000>;
349*4882a593Smuzhiyun	};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun	partition@100000 {
352*4882a593Smuzhiyun		label = "kernel-1";
353*4882a593Smuzhiyun		reg = <0x00100000 0x00800000>;
354*4882a593Smuzhiyun	};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun	partition@900000 {
357*4882a593Smuzhiyun		label = "rootfs-1";
358*4882a593Smuzhiyun		reg = <0x00900000 0x07100000>;
359*4882a593Smuzhiyun	};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun	partition@7a00000 {
362*4882a593Smuzhiyun		label = "kernel-2";
363*4882a593Smuzhiyun		reg = <0x07a00000 0x00800000>;
364*4882a593Smuzhiyun	};
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun	partition@8200000 {
367*4882a593Smuzhiyun		label = "rootfs-2";
368*4882a593Smuzhiyun		reg = <0x08200000 0x07100000>;
369*4882a593Smuzhiyun	};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun	partition@f300000 {
372*4882a593Smuzhiyun		label = "default_sw";
373*4882a593Smuzhiyun		reg = <0x0f300000 0x07900000>;
374*4882a593Smuzhiyun	};
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun	partition@16c00000 {
377*4882a593Smuzhiyun		label = "logs";
378*4882a593Smuzhiyun		reg = <0x16c00000 0x01800000>;
379*4882a593Smuzhiyun	};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun	partition@18400000 {
382*4882a593Smuzhiyun		label = "preset_cfg";
383*4882a593Smuzhiyun		reg = <0x18400000 0x00100000>;
384*4882a593Smuzhiyun	};
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun	partition@18500000 {
387*4882a593Smuzhiyun		label = "adsl";
388*4882a593Smuzhiyun		reg = <0x18500000 0x00100000>;
389*4882a593Smuzhiyun	};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun	partition@18600000 {
392*4882a593Smuzhiyun		label = "storage";
393*4882a593Smuzhiyun		reg = <0x18600000 0x07a00000>;
394*4882a593Smuzhiyun	};
395*4882a593Smuzhiyun};
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun&rtc {
398*4882a593Smuzhiyun	status = "disabled";
399*4882a593Smuzhiyun};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun&pciec {
402*4882a593Smuzhiyun	status = "okay";
403*4882a593Smuzhiyun};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun&pcie0 {
406*4882a593Smuzhiyun	status = "okay";
407*4882a593Smuzhiyun};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun&sata_phy0 {
410*4882a593Smuzhiyun	status = "disabled";
411*4882a593Smuzhiyun};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun&sata_phy1 {
414*4882a593Smuzhiyun	status = "disabled";
415*4882a593Smuzhiyun};
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun&usb0 {
418*4882a593Smuzhiyun	#address-cells = <1>;
419*4882a593Smuzhiyun	#size-cells = <0>;
420*4882a593Smuzhiyun	status = "okay";
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun	port@1 {
423*4882a593Smuzhiyun		#address-cells = <1>;
424*4882a593Smuzhiyun		#size-cells = <0>;
425*4882a593Smuzhiyun		reg = <1>;
426*4882a593Smuzhiyun		#trigger-source-cells = <0>;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun		hub_port1: port@1 {
429*4882a593Smuzhiyun			reg = <1>;
430*4882a593Smuzhiyun			#trigger-source-cells = <0>;
431*4882a593Smuzhiyun		};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun		hub_port3: port@3 {
434*4882a593Smuzhiyun			reg = <3>;
435*4882a593Smuzhiyun			#trigger-source-cells = <0>;
436*4882a593Smuzhiyun		};
437*4882a593Smuzhiyun	};
438*4882a593Smuzhiyun};
439