xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/kirkwood-98dx4122.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/ {
3*4882a593Smuzhiyun	mbus@f1000000 {
4*4882a593Smuzhiyun		pciec: pcie@82000000 {
5*4882a593Smuzhiyun			compatible = "marvell,kirkwood-pcie";
6*4882a593Smuzhiyun			status = "disabled";
7*4882a593Smuzhiyun			device_type = "pci";
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun			#address-cells = <3>;
10*4882a593Smuzhiyun			#size-cells = <2>;
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun			bus-range = <0x00 0xff>;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun			ranges =
15*4882a593Smuzhiyun			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16*4882a593Smuzhiyun				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
17*4882a593Smuzhiyun				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun			pcie0: pcie@1,0 {
20*4882a593Smuzhiyun				device_type = "pci";
21*4882a593Smuzhiyun				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22*4882a593Smuzhiyun				reg = <0x0800 0 0 0 0>;
23*4882a593Smuzhiyun				#address-cells = <3>;
24*4882a593Smuzhiyun				#size-cells = <2>;
25*4882a593Smuzhiyun				#interrupt-cells = <1>;
26*4882a593Smuzhiyun				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27*4882a593Smuzhiyun					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
28*4882a593Smuzhiyun				bus-range = <0x00 0xff>;
29*4882a593Smuzhiyun				interrupt-map-mask = <0 0 0 0>;
30*4882a593Smuzhiyun				interrupt-map = <0 0 0 0 &intc 9>;
31*4882a593Smuzhiyun				marvell,pcie-port = <0>;
32*4882a593Smuzhiyun				marvell,pcie-lane = <0>;
33*4882a593Smuzhiyun				clocks = <&gate_clk 2>;
34*4882a593Smuzhiyun				status = "disabled";
35*4882a593Smuzhiyun			};
36*4882a593Smuzhiyun		};
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	ocp@f1000000 {
40*4882a593Smuzhiyun		pinctrl: pin-controller@10000 {
41*4882a593Smuzhiyun			compatible = "marvell,98dx4122-pinctrl";
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		};
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun&sata_phy0 {
48*4882a593Smuzhiyun	status = "disabled";
49*4882a593Smuzhiyun};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun&sata_phy1 {
52*4882a593Smuzhiyun	status = "disabled";
53*4882a593Smuzhiyun};
54