xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/kirkwood-6282.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/ {
3*4882a593Smuzhiyun	mbus@f1000000 {
4*4882a593Smuzhiyun		pciec: pcie@82000000 {
5*4882a593Smuzhiyun			compatible = "marvell,kirkwood-pcie";
6*4882a593Smuzhiyun			status = "disabled";
7*4882a593Smuzhiyun			device_type = "pci";
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun			#address-cells = <3>;
10*4882a593Smuzhiyun			#size-cells = <2>;
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun			bus-range = <0x00 0xff>;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun			ranges =
15*4882a593Smuzhiyun			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16*4882a593Smuzhiyun			        0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
17*4882a593Smuzhiyun				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
18*4882a593Smuzhiyun				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
19*4882a593Smuzhiyun				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
20*4882a593Smuzhiyun				0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0       1 0 /* Port 1.0 MEM */
21*4882a593Smuzhiyun				0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0       1 0 /* Port 1.0 IO  */>;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun			pcie0: pcie@1,0 {
24*4882a593Smuzhiyun				device_type = "pci";
25*4882a593Smuzhiyun				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
26*4882a593Smuzhiyun				reg = <0x0800 0 0 0 0>;
27*4882a593Smuzhiyun				#address-cells = <3>;
28*4882a593Smuzhiyun				#size-cells = <2>;
29*4882a593Smuzhiyun				#interrupt-cells = <1>;
30*4882a593Smuzhiyun				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
31*4882a593Smuzhiyun					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
32*4882a593Smuzhiyun				bus-range = <0x00 0xff>;
33*4882a593Smuzhiyun				interrupt-map-mask = <0 0 0 0>;
34*4882a593Smuzhiyun				interrupt-map = <0 0 0 0 &intc 9>;
35*4882a593Smuzhiyun				marvell,pcie-port = <0>;
36*4882a593Smuzhiyun				marvell,pcie-lane = <0>;
37*4882a593Smuzhiyun				clocks = <&gate_clk 2>;
38*4882a593Smuzhiyun				status = "disabled";
39*4882a593Smuzhiyun			};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun			pcie1: pcie@2,0 {
42*4882a593Smuzhiyun				device_type = "pci";
43*4882a593Smuzhiyun				assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
44*4882a593Smuzhiyun				reg = <0x1000 0 0 0 0>;
45*4882a593Smuzhiyun				#address-cells = <3>;
46*4882a593Smuzhiyun				#size-cells = <2>;
47*4882a593Smuzhiyun				#interrupt-cells = <1>;
48*4882a593Smuzhiyun				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
49*4882a593Smuzhiyun					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
50*4882a593Smuzhiyun				bus-range = <0x00 0xff>;
51*4882a593Smuzhiyun				interrupt-map-mask = <0 0 0 0>;
52*4882a593Smuzhiyun				interrupt-map = <0 0 0 0 &intc 10>;
53*4882a593Smuzhiyun				marvell,pcie-port = <1>;
54*4882a593Smuzhiyun				marvell,pcie-lane = <0>;
55*4882a593Smuzhiyun				clocks = <&gate_clk 18>;
56*4882a593Smuzhiyun				status = "disabled";
57*4882a593Smuzhiyun			};
58*4882a593Smuzhiyun		};
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun	ocp@f1000000 {
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		pinctrl: pin-controller@10000 {
63*4882a593Smuzhiyun			compatible = "marvell,88f6282-pinctrl";
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun			pmx_sata0: pmx-sata0 {
66*4882a593Smuzhiyun				marvell,pins = "mpp5", "mpp21", "mpp23";
67*4882a593Smuzhiyun				marvell,function = "sata0";
68*4882a593Smuzhiyun			};
69*4882a593Smuzhiyun			pmx_sata1: pmx-sata1 {
70*4882a593Smuzhiyun				marvell,pins = "mpp4", "mpp20", "mpp22";
71*4882a593Smuzhiyun				marvell,function = "sata1";
72*4882a593Smuzhiyun			};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun			/*
75*4882a593Smuzhiyun			 * Default I2C1 pinctrl setting on mpp36/mpp37,
76*4882a593Smuzhiyun			 * overwrite marvell,pins on board level if required.
77*4882a593Smuzhiyun			 */
78*4882a593Smuzhiyun			pmx_twsi1: pmx-twsi1 {
79*4882a593Smuzhiyun				marvell,pins = "mpp36", "mpp37";
80*4882a593Smuzhiyun				marvell,function = "twsi1";
81*4882a593Smuzhiyun			};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun			pmx_sdio: pmx-sdio {
84*4882a593Smuzhiyun				marvell,pins = "mpp12", "mpp13", "mpp14",
85*4882a593Smuzhiyun					       "mpp15", "mpp16", "mpp17";
86*4882a593Smuzhiyun				marvell,function = "sdio";
87*4882a593Smuzhiyun			};
88*4882a593Smuzhiyun		};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun		thermal: thermal@10078 {
91*4882a593Smuzhiyun			compatible = "marvell,kirkwood-thermal";
92*4882a593Smuzhiyun			reg = <0x10078 0x4>;
93*4882a593Smuzhiyun			status = "okay";
94*4882a593Smuzhiyun		};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun		rtc: rtc@10300 {
97*4882a593Smuzhiyun			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
98*4882a593Smuzhiyun			reg = <0x10300 0x20>;
99*4882a593Smuzhiyun			interrupts = <53>;
100*4882a593Smuzhiyun			clocks = <&gate_clk 7>;
101*4882a593Smuzhiyun		};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun		i2c1: i2c@11100 {
104*4882a593Smuzhiyun			compatible = "marvell,mv64xxx-i2c";
105*4882a593Smuzhiyun			reg = <0x11100 0x20>;
106*4882a593Smuzhiyun			#address-cells = <1>;
107*4882a593Smuzhiyun			#size-cells = <0>;
108*4882a593Smuzhiyun			interrupts = <32>;
109*4882a593Smuzhiyun			clock-frequency = <100000>;
110*4882a593Smuzhiyun			clocks = <&gate_clk 7>;
111*4882a593Smuzhiyun			pinctrl-0 = <&pmx_twsi1>;
112*4882a593Smuzhiyun			pinctrl-names = "default";
113*4882a593Smuzhiyun			status = "disabled";
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun		sata: sata@80000 {
117*4882a593Smuzhiyun			compatible = "marvell,orion-sata";
118*4882a593Smuzhiyun			reg = <0x80000 0x5000>;
119*4882a593Smuzhiyun			interrupts = <21>;
120*4882a593Smuzhiyun			clocks = <&gate_clk 14>, <&gate_clk 15>;
121*4882a593Smuzhiyun			clock-names = "0", "1";
122*4882a593Smuzhiyun			phys = <&sata_phy0>, <&sata_phy1>;
123*4882a593Smuzhiyun			phy-names = "port0", "port1";
124*4882a593Smuzhiyun			status = "disabled";
125*4882a593Smuzhiyun		};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun		sdio: mvsdio@90000 {
128*4882a593Smuzhiyun			compatible = "marvell,orion-sdio";
129*4882a593Smuzhiyun			reg = <0x90000 0x200>;
130*4882a593Smuzhiyun			interrupts = <28>;
131*4882a593Smuzhiyun			clocks = <&gate_clk 4>;
132*4882a593Smuzhiyun			pinctrl-0 = <&pmx_sdio>;
133*4882a593Smuzhiyun			pinctrl-names = "default";
134*4882a593Smuzhiyun			bus-width = <4>;
135*4882a593Smuzhiyun			cap-sdio-irq;
136*4882a593Smuzhiyun			cap-sd-highspeed;
137*4882a593Smuzhiyun			cap-mmc-highspeed;
138*4882a593Smuzhiyun			status = "disabled";
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun};
142