1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/ { 3*4882a593Smuzhiyun mbus@f1000000 { 4*4882a593Smuzhiyun pciec: pcie@82000000 { 5*4882a593Smuzhiyun compatible = "marvell,kirkwood-pcie"; 6*4882a593Smuzhiyun status = "disabled"; 7*4882a593Smuzhiyun device_type = "pci"; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #address-cells = <3>; 10*4882a593Smuzhiyun #size-cells = <2>; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun bus-range = <0x00 0xff>; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun ranges = 15*4882a593Smuzhiyun <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16*4882a593Smuzhiyun 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17*4882a593Smuzhiyun 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun pcie0: pcie@1,0 { 20*4882a593Smuzhiyun device_type = "pci"; 21*4882a593Smuzhiyun assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22*4882a593Smuzhiyun reg = <0x0800 0 0 0 0>; 23*4882a593Smuzhiyun #address-cells = <3>; 24*4882a593Smuzhiyun #size-cells = <2>; 25*4882a593Smuzhiyun #interrupt-cells = <1>; 26*4882a593Smuzhiyun ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27*4882a593Smuzhiyun 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28*4882a593Smuzhiyun bus-range = <0x00 0xff>; 29*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 30*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &intc 9>; 31*4882a593Smuzhiyun marvell,pcie-port = <0>; 32*4882a593Smuzhiyun marvell,pcie-lane = <0>; 33*4882a593Smuzhiyun clocks = <&gate_clk 2>; 34*4882a593Smuzhiyun status = "disabled"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun ocp@f1000000 { 40*4882a593Smuzhiyun pinctrl: pin-controller@10000 { 41*4882a593Smuzhiyun compatible = "marvell,88f6192-pinctrl"; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun pmx_sata0: pmx-sata0 { 44*4882a593Smuzhiyun marvell,pins = "mpp5", "mpp21", "mpp23"; 45*4882a593Smuzhiyun marvell,function = "sata0"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun pmx_sata1: pmx-sata1 { 48*4882a593Smuzhiyun marvell,pins = "mpp4", "mpp20", "mpp22"; 49*4882a593Smuzhiyun marvell,function = "sata1"; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun pmx_sdio: pmx-sdio { 52*4882a593Smuzhiyun marvell,pins = "mpp12", "mpp13", "mpp14", 53*4882a593Smuzhiyun "mpp15", "mpp16", "mpp17"; 54*4882a593Smuzhiyun marvell,function = "sdio"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun rtc: rtc@10300 { 59*4882a593Smuzhiyun compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; 60*4882a593Smuzhiyun reg = <0x10300 0x20>; 61*4882a593Smuzhiyun interrupts = <53>; 62*4882a593Smuzhiyun clocks = <&gate_clk 7>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun sata: sata@80000 { 66*4882a593Smuzhiyun compatible = "marvell,orion-sata"; 67*4882a593Smuzhiyun reg = <0x80000 0x5000>; 68*4882a593Smuzhiyun interrupts = <21>; 69*4882a593Smuzhiyun clocks = <&gate_clk 14>, <&gate_clk 15>; 70*4882a593Smuzhiyun clock-names = "0", "1"; 71*4882a593Smuzhiyun phys = <&sata_phy0>, <&sata_phy1>; 72*4882a593Smuzhiyun phy-names = "port0", "port1"; 73*4882a593Smuzhiyun status = "disabled"; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun sdio: mvsdio@90000 { 77*4882a593Smuzhiyun compatible = "marvell,orion-sdio"; 78*4882a593Smuzhiyun reg = <0x90000 0x200>; 79*4882a593Smuzhiyun interrupts = <28>; 80*4882a593Smuzhiyun clocks = <&gate_clk 4>; 81*4882a593Smuzhiyun bus-width = <4>; 82*4882a593Smuzhiyun cap-sdio-irq; 83*4882a593Smuzhiyun cap-sd-highspeed; 84*4882a593Smuzhiyun cap-mmc-highspeed; 85*4882a593Smuzhiyun status = "disabled"; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun}; 89