1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Keystone 2 Lamarr EVM device tree 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "keystone.dtsi" 10*4882a593Smuzhiyun#include "keystone-k2l.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; 14*4882a593Smuzhiyun model = "Texas Instruments Keystone 2 Lamarr EVM"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun reserved-memory { 17*4882a593Smuzhiyun #address-cells = <2>; 18*4882a593Smuzhiyun #size-cells = <2>; 19*4882a593Smuzhiyun ranges; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun dsp_common_memory: dsp-common-memory@81f800000 { 22*4882a593Smuzhiyun compatible = "shared-dma-pool"; 23*4882a593Smuzhiyun reg = <0x00000008 0x1f800000 0x00000000 0x800000>; 24*4882a593Smuzhiyun reusable; 25*4882a593Smuzhiyun status = "okay"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&soc0 { 31*4882a593Smuzhiyun clocks { 32*4882a593Smuzhiyun refclksys: refclksys { 33*4882a593Smuzhiyun #clock-cells = <0>; 34*4882a593Smuzhiyun compatible = "fixed-clock"; 35*4882a593Smuzhiyun clock-frequency = <122880000>; 36*4882a593Smuzhiyun clock-output-names = "refclk-sys"; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&usb_phy { 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun&keystone_usb0 { 46*4882a593Smuzhiyun status = "okay"; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&usb0 { 50*4882a593Smuzhiyun dr_mode = "host"; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun&i2c0 { 54*4882a593Smuzhiyun dtt@50 { 55*4882a593Smuzhiyun compatible = "atmel,24c1024"; 56*4882a593Smuzhiyun reg = <0x50>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun}; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun&aemif { 61*4882a593Smuzhiyun cs0 { 62*4882a593Smuzhiyun #address-cells = <2>; 63*4882a593Smuzhiyun #size-cells = <1>; 64*4882a593Smuzhiyun clock-ranges; 65*4882a593Smuzhiyun ranges; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun ti,cs-chipselect = <0>; 68*4882a593Smuzhiyun /* all timings in nanoseconds */ 69*4882a593Smuzhiyun ti,cs-min-turnaround-ns = <12>; 70*4882a593Smuzhiyun ti,cs-read-hold-ns = <6>; 71*4882a593Smuzhiyun ti,cs-read-strobe-ns = <23>; 72*4882a593Smuzhiyun ti,cs-read-setup-ns = <9>; 73*4882a593Smuzhiyun ti,cs-write-hold-ns = <8>; 74*4882a593Smuzhiyun ti,cs-write-strobe-ns = <23>; 75*4882a593Smuzhiyun ti,cs-write-setup-ns = <8>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun nand@0,0 { 78*4882a593Smuzhiyun compatible = "ti,keystone-nand","ti,davinci-nand"; 79*4882a593Smuzhiyun #address-cells = <1>; 80*4882a593Smuzhiyun #size-cells = <1>; 81*4882a593Smuzhiyun reg = <0 0 0x4000000 82*4882a593Smuzhiyun 1 0 0x0000100>; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun ti,davinci-chipselect = <0>; 85*4882a593Smuzhiyun ti,davinci-mask-ale = <0x2000>; 86*4882a593Smuzhiyun ti,davinci-mask-cle = <0x4000>; 87*4882a593Smuzhiyun ti,davinci-mask-chipsel = <0>; 88*4882a593Smuzhiyun nand-ecc-mode = "hw"; 89*4882a593Smuzhiyun ti,davinci-ecc-bits = <4>; 90*4882a593Smuzhiyun nand-on-flash-bbt; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun partition@0 { 93*4882a593Smuzhiyun label = "u-boot"; 94*4882a593Smuzhiyun reg = <0x0 0x100000>; 95*4882a593Smuzhiyun read-only; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun partition@100000 { 99*4882a593Smuzhiyun label = "params"; 100*4882a593Smuzhiyun reg = <0x100000 0x80000>; 101*4882a593Smuzhiyun read-only; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun partition@180000 { 105*4882a593Smuzhiyun label = "ubifs"; 106*4882a593Smuzhiyun reg = <0x180000 0x7FE80000>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&spi0 { 113*4882a593Smuzhiyun nor_flash: n25q128a11@0 { 114*4882a593Smuzhiyun #address-cells = <1>; 115*4882a593Smuzhiyun #size-cells = <1>; 116*4882a593Smuzhiyun compatible = "Micron,n25q128a11"; 117*4882a593Smuzhiyun spi-max-frequency = <54000000>; 118*4882a593Smuzhiyun m25p,fast-read; 119*4882a593Smuzhiyun reg = <0>; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun partition@0 { 122*4882a593Smuzhiyun label = "u-boot-spl"; 123*4882a593Smuzhiyun reg = <0x0 0x80000>; 124*4882a593Smuzhiyun read-only; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun partition@1 { 128*4882a593Smuzhiyun label = "misc"; 129*4882a593Smuzhiyun reg = <0x80000 0xf80000>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&mdio { 135*4882a593Smuzhiyun status = "ok"; 136*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 137*4882a593Smuzhiyun compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; 138*4882a593Smuzhiyun reg = <0>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun ethphy1: ethernet-phy@1 { 142*4882a593Smuzhiyun compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; 143*4882a593Smuzhiyun reg = <1>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun}; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun&dsp0 { 148*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 149*4882a593Smuzhiyun status = "okay"; 150*4882a593Smuzhiyun}; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun&dsp1 { 153*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 154*4882a593Smuzhiyun status = "okay"; 155*4882a593Smuzhiyun}; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun&dsp2 { 158*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 159*4882a593Smuzhiyun status = "okay"; 160*4882a593Smuzhiyun}; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun&dsp3 { 163*4882a593Smuzhiyun memory-region = <&dsp_common_memory>; 164*4882a593Smuzhiyun status = "okay"; 165*4882a593Smuzhiyun}; 166