1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2019 NXP 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "imx7ulp.dtsi" 8*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Embedded Artists i.MX7ULP COM"; 12*4882a593Smuzhiyun compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun chosen { 15*4882a593Smuzhiyun stdout-path = &lpuart4; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun memory@60000000 { 19*4882a593Smuzhiyun device_type = "memory"; 20*4882a593Smuzhiyun reg = <0x60000000 0x4000000>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun}; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun&lpuart4 { 25*4882a593Smuzhiyun pinctrl-names = "default"; 26*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_lpuart4>; 27*4882a593Smuzhiyun status = "okay"; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&usbotg1 { 31*4882a593Smuzhiyun pinctrl-names = "default"; 32*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg1_id>; 33*4882a593Smuzhiyun srp-disable; 34*4882a593Smuzhiyun hnp-disable; 35*4882a593Smuzhiyun adp-disable; 36*4882a593Smuzhiyun status = "okay"; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&usdhc0 { 40*4882a593Smuzhiyun assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; 41*4882a593Smuzhiyun assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; 42*4882a593Smuzhiyun pinctrl-names = "default"; 43*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc0>; 44*4882a593Smuzhiyun non-removable; 45*4882a593Smuzhiyun bus-width = <8>; 46*4882a593Smuzhiyun no-1-8-v; 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&iomuxc1 { 51*4882a593Smuzhiyun pinctrl_lpuart4: lpuart4grp { 52*4882a593Smuzhiyun fsl,pins = < 53*4882a593Smuzhiyun IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 54*4882a593Smuzhiyun IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 55*4882a593Smuzhiyun >; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun pinctrl_usbotg1_id: otg1idgrp { 59*4882a593Smuzhiyun fsl,pins = < 60*4882a593Smuzhiyun IMX7ULP_PAD_PTC13__USB0_ID 0x10003 61*4882a593Smuzhiyun >; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun pinctrl_usdhc0: usdhc0grp { 65*4882a593Smuzhiyun fsl,pins = < 66*4882a593Smuzhiyun IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 67*4882a593Smuzhiyun IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 68*4882a593Smuzhiyun IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 69*4882a593Smuzhiyun IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 70*4882a593Smuzhiyun IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 71*4882a593Smuzhiyun IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 72*4882a593Smuzhiyun IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 73*4882a593Smuzhiyun IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 74*4882a593Smuzhiyun IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 75*4882a593Smuzhiyun IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 76*4882a593Smuzhiyun IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 77*4882a593Smuzhiyun >; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun}; 80