1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2016 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun#include "imx6ul.dtsi" 6*4882a593Smuzhiyun#include "imx6ull-pinfunc.h" 7*4882a593Smuzhiyun#include "imx6ull-pinfunc-snvs.h" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/* Delete UART8 in AIPS-1 (i.MX6UL specific) */ 10*4882a593Smuzhiyun/delete-node/ &uart8; 11*4882a593Smuzhiyun/* Delete CAAM node in AIPS-2 (i.MX6UL specific) */ 12*4882a593Smuzhiyun/delete-node/ &crypto; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun&cpu0 { 15*4882a593Smuzhiyun clock-frequency = <900000000>; 16*4882a593Smuzhiyun operating-points = < 17*4882a593Smuzhiyun /* kHz uV */ 18*4882a593Smuzhiyun 900000 1275000 19*4882a593Smuzhiyun 792000 1225000 20*4882a593Smuzhiyun 528000 1175000 21*4882a593Smuzhiyun 396000 1025000 22*4882a593Smuzhiyun 198000 950000 23*4882a593Smuzhiyun >; 24*4882a593Smuzhiyun fsl,soc-operating-points = < 25*4882a593Smuzhiyun /* KHz uV */ 26*4882a593Smuzhiyun 900000 1250000 27*4882a593Smuzhiyun 792000 1175000 28*4882a593Smuzhiyun 528000 1175000 29*4882a593Smuzhiyun 396000 1175000 30*4882a593Smuzhiyun 198000 1175000 31*4882a593Smuzhiyun >; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&ocotp { 35*4882a593Smuzhiyun compatible = "fsl,imx6ull-ocotp", "syscon"; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun&pxp { 39*4882a593Smuzhiyun compatible = "fsl,imx6ull-pxp"; 40*4882a593Smuzhiyun interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 41*4882a593Smuzhiyun <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&usdhc1 { 45*4882a593Smuzhiyun compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&usdhc2 { 49*4882a593Smuzhiyun compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun/ { 53*4882a593Smuzhiyun soc { 54*4882a593Smuzhiyun aips3: bus@2200000 { 55*4882a593Smuzhiyun compatible = "fsl,aips-bus", "simple-bus"; 56*4882a593Smuzhiyun #address-cells = <1>; 57*4882a593Smuzhiyun #size-cells = <1>; 58*4882a593Smuzhiyun reg = <0x02200000 0x100000>; 59*4882a593Smuzhiyun ranges; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun dcp: crypto@2280000 { 62*4882a593Smuzhiyun compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp"; 63*4882a593Smuzhiyun reg = <0x02280000 0x4000>; 64*4882a593Smuzhiyun interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 65*4882a593Smuzhiyun <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 66*4882a593Smuzhiyun <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 67*4882a593Smuzhiyun clocks = <&clks IMX6ULL_CLK_DCP_CLK>; 68*4882a593Smuzhiyun clock-names = "dcp"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun rngb: rng@2284000 { 72*4882a593Smuzhiyun compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb"; 73*4882a593Smuzhiyun reg = <0x02284000 0x4000>; 74*4882a593Smuzhiyun interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 75*4882a593Smuzhiyun clocks = <&clks IMX6UL_CLK_DUMMY>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun iomuxc_snvs: iomuxc-snvs@2290000 { 79*4882a593Smuzhiyun compatible = "fsl,imx6ull-iomuxc-snvs"; 80*4882a593Smuzhiyun reg = <0x02290000 0x4000>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun uart8: serial@2288000 { 84*4882a593Smuzhiyun compatible = "fsl,imx6ul-uart", 85*4882a593Smuzhiyun "fsl,imx6q-uart"; 86*4882a593Smuzhiyun reg = <0x02288000 0x4000>; 87*4882a593Smuzhiyun interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 88*4882a593Smuzhiyun clocks = <&clks IMX6UL_CLK_UART8_IPG>, 89*4882a593Smuzhiyun <&clks IMX6UL_CLK_UART8_SERIAL>; 90*4882a593Smuzhiyun clock-names = "ipg", "per"; 91*4882a593Smuzhiyun status = "disabled"; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun}; 96