xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/imx6ul-imx6ull-opos6uldev.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR MIT
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2019 Armadeus Systems <support@armadeus.com>
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/ {
6*4882a593Smuzhiyun	chosen {
7*4882a593Smuzhiyun		stdout-path = &uart1;
8*4882a593Smuzhiyun	};
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun	backlight: backlight {
11*4882a593Smuzhiyun		compatible = "pwm-backlight";
12*4882a593Smuzhiyun		pwms = <&pwm3 0 191000>;
13*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
14*4882a593Smuzhiyun		default-brightness-level = <7>;
15*4882a593Smuzhiyun		power-supply = <&reg_5v>;
16*4882a593Smuzhiyun		status = "okay";
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	gpio-keys {
20*4882a593Smuzhiyun		compatible = "gpio-keys";
21*4882a593Smuzhiyun		pinctrl-names = "default";
22*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_keys>;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun		user-button {
25*4882a593Smuzhiyun			label = "User button";
26*4882a593Smuzhiyun			gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
27*4882a593Smuzhiyun			linux,code = <BTN_MISC>;
28*4882a593Smuzhiyun			wakeup-source;
29*4882a593Smuzhiyun		};
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	leds {
33*4882a593Smuzhiyun		compatible = "gpio-leds";
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		user-led {
36*4882a593Smuzhiyun			label = "User";
37*4882a593Smuzhiyun			pinctrl-names = "default";
38*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_led>;
39*4882a593Smuzhiyun			gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
40*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun	};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun	onewire {
45*4882a593Smuzhiyun		compatible = "w1-gpio";
46*4882a593Smuzhiyun		pinctrl-names = "default";
47*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_w1>;
48*4882a593Smuzhiyun		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	panel: panel {
52*4882a593Smuzhiyun		compatible = "armadeus,st0700-adapt";
53*4882a593Smuzhiyun		power-supply = <&reg_3v3>;
54*4882a593Smuzhiyun		backlight = <&backlight>;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun		port {
57*4882a593Smuzhiyun			panel_in: endpoint {
58*4882a593Smuzhiyun				remote-endpoint = <&lcdif_out>;
59*4882a593Smuzhiyun			};
60*4882a593Smuzhiyun		};
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	reg_5v: regulator-5v {
64*4882a593Smuzhiyun		compatible = "regulator-fixed";
65*4882a593Smuzhiyun		regulator-name = "5V";
66*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
67*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	reg_usbotg1_vbus: regulator-usbotg1vbus {
71*4882a593Smuzhiyun		compatible = "regulator-fixed";
72*4882a593Smuzhiyun		regulator-name = "usbotg1vbus";
73*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
74*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
75*4882a593Smuzhiyun		pinctrl-names = "default";
76*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbotg1_vbus>;
77*4882a593Smuzhiyun		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
78*4882a593Smuzhiyun		enable-active-high;
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	reg_usbotg2_vbus: regulator-usbotg2vbus {
82*4882a593Smuzhiyun		compatible = "regulator-fixed";
83*4882a593Smuzhiyun		regulator-name = "usbotg2vbus";
84*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
85*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
86*4882a593Smuzhiyun		pinctrl-names = "default";
87*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbotg2_vbus>;
88*4882a593Smuzhiyun		gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
89*4882a593Smuzhiyun		enable-active-high;
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun&adc1 {
94*4882a593Smuzhiyun	vref-supply = <&reg_3v3>;
95*4882a593Smuzhiyun	status = "okay";
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun&can1 {
99*4882a593Smuzhiyun	pinctrl-names = "default";
100*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
101*4882a593Smuzhiyun	xceiver-supply = <&reg_5v>;
102*4882a593Smuzhiyun	status = "okay";
103*4882a593Smuzhiyun};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun&can2 {
106*4882a593Smuzhiyun	pinctrl-names = "default";
107*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
108*4882a593Smuzhiyun	xceiver-supply = <&reg_5v>;
109*4882a593Smuzhiyun	status = "okay";
110*4882a593Smuzhiyun};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun&ecspi4 {
113*4882a593Smuzhiyun	pinctrl-names = "default";
114*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi4>;
115*4882a593Smuzhiyun	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
116*4882a593Smuzhiyun	status = "okay";
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun	spidev0: spi@0 {
119*4882a593Smuzhiyun		compatible = "spidev";
120*4882a593Smuzhiyun		reg = <0>;
121*4882a593Smuzhiyun		spi-max-frequency = <5000000>;
122*4882a593Smuzhiyun	};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	spidev1: spi@1 {
125*4882a593Smuzhiyun		compatible = "spidev";
126*4882a593Smuzhiyun		reg = <1>;
127*4882a593Smuzhiyun		spi-max-frequency = <5000000>;
128*4882a593Smuzhiyun	};
129*4882a593Smuzhiyun};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun&i2c1 {
132*4882a593Smuzhiyun	pinctrl-names = "default";
133*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
134*4882a593Smuzhiyun	clock-frequency = <400000>;
135*4882a593Smuzhiyun	status = "okay";
136*4882a593Smuzhiyun};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun&i2c2 {
139*4882a593Smuzhiyun	pinctrl-names = "default";
140*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
141*4882a593Smuzhiyun	clock-frequency = <400000>;
142*4882a593Smuzhiyun	status = "okay";
143*4882a593Smuzhiyun};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun&lcdif {
146*4882a593Smuzhiyun	pinctrl-names = "default";
147*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lcdif>;
148*4882a593Smuzhiyun	status = "okay";
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	port {
151*4882a593Smuzhiyun		lcdif_out: endpoint {
152*4882a593Smuzhiyun			remote-endpoint = <&panel_in>;
153*4882a593Smuzhiyun		};
154*4882a593Smuzhiyun	};
155*4882a593Smuzhiyun};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun&pwm3 {
158*4882a593Smuzhiyun	#pwm-cells = <2>;
159*4882a593Smuzhiyun	pinctrl-names = "default";
160*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
161*4882a593Smuzhiyun	status = "okay";
162*4882a593Smuzhiyun};
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun&snvs_pwrkey {
165*4882a593Smuzhiyun	status = "disabled";
166*4882a593Smuzhiyun};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun&tsc {
169*4882a593Smuzhiyun	pinctrl-names = "default";
170*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_tsc>;
171*4882a593Smuzhiyun	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
172*4882a593Smuzhiyun	measure-delay-time = <0xffff>;
173*4882a593Smuzhiyun	pre-charge-time = <0xffff>;
174*4882a593Smuzhiyun	status = "okay";
175*4882a593Smuzhiyun};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun&uart1 {
178*4882a593Smuzhiyun	pinctrl-names = "default";
179*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
180*4882a593Smuzhiyun	status = "okay";
181*4882a593Smuzhiyun};
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun&uart2 {
184*4882a593Smuzhiyun	pinctrl-names = "default";
185*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
186*4882a593Smuzhiyun	status = "okay";
187*4882a593Smuzhiyun};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun&usbotg1 {
190*4882a593Smuzhiyun	pinctrl-names = "default";
191*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg1_id>;
192*4882a593Smuzhiyun	vbus-supply = <&reg_usbotg1_vbus>;
193*4882a593Smuzhiyun	dr_mode = "otg";
194*4882a593Smuzhiyun	disable-over-current;
195*4882a593Smuzhiyun	status = "okay";
196*4882a593Smuzhiyun};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun&usbotg2 {
199*4882a593Smuzhiyun	vbus-supply = <&reg_usbotg2_vbus>;
200*4882a593Smuzhiyun	dr_mode = "host";
201*4882a593Smuzhiyun	disable-over-current;
202*4882a593Smuzhiyun	status = "okay";
203*4882a593Smuzhiyun};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun&iomuxc {
206*4882a593Smuzhiyun	pinctrl-names = "default";
207*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_gpios>;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun	pinctrl_ecspi4: ecspi4grp {
210*4882a593Smuzhiyun		fsl,pins = <
211*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK	0x1b0b0
212*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI	0x1b0b0
213*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA06__ECSPI4_MISO	0x1b0b0
214*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA01__GPIO4_IO03	0x1b0b0
215*4882a593Smuzhiyun			MX6UL_PAD_NAND_DATA07__GPIO4_IO09	0x1b0b0
216*4882a593Smuzhiyun		>;
217*4882a593Smuzhiyun	};
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun	pinctrl_flexcan1: flexcan1grp {
220*4882a593Smuzhiyun		fsl,pins = <
221*4882a593Smuzhiyun			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
222*4882a593Smuzhiyun			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
223*4882a593Smuzhiyun		>;
224*4882a593Smuzhiyun	};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun	pinctrl_flexcan2: flexcan2grp {
227*4882a593Smuzhiyun		fsl,pins = <
228*4882a593Smuzhiyun			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x0b0b0
229*4882a593Smuzhiyun			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x0b0b0
230*4882a593Smuzhiyun		>;
231*4882a593Smuzhiyun	};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun	pinctrl_gpios: gpiosgrp {
234*4882a593Smuzhiyun		fsl,pins = <
235*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x0b0b0
236*4882a593Smuzhiyun			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x0b0b0
237*4882a593Smuzhiyun			MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x0b0b0
238*4882a593Smuzhiyun			MX6UL_PAD_NAND_RE_B__GPIO4_IO00		0x0b0b0
239*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0x0b0b0
240*4882a593Smuzhiyun			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x0b0b0
241*4882a593Smuzhiyun			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x0b0b0
242*4882a593Smuzhiyun			MX6UL_PAD_NAND_WE_B__GPIO4_IO01		0x0b0b0
243*4882a593Smuzhiyun		>;
244*4882a593Smuzhiyun	};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun	pinctrl_gpio_keys: gpiokeysgrp {
247*4882a593Smuzhiyun		fsl,pins = <
248*4882a593Smuzhiyun			MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11	0x0b0b0
249*4882a593Smuzhiyun		>;
250*4882a593Smuzhiyun	};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
253*4882a593Smuzhiyun		fsl,pins = <
254*4882a593Smuzhiyun			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA	0x4001b8b0
255*4882a593Smuzhiyun			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL	0x4001b8b0
256*4882a593Smuzhiyun		>;
257*4882a593Smuzhiyun	};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
260*4882a593Smuzhiyun		fsl,pins = <
261*4882a593Smuzhiyun			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
262*4882a593Smuzhiyun			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
263*4882a593Smuzhiyun		>;
264*4882a593Smuzhiyun	};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun	pinctrl_lcdif: lcdifgrp {
267*4882a593Smuzhiyun		fsl,pins = <
268*4882a593Smuzhiyun			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x100b1
269*4882a593Smuzhiyun			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x100b1
270*4882a593Smuzhiyun			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x100b1
271*4882a593Smuzhiyun			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x100b1
272*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x100b1
273*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x100b1
274*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x100b1
275*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x100b1
276*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x100b1
277*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x100b1
278*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x100b1
279*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x100b1
280*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x100b1
281*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x100b1
282*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x100b1
283*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x100b1
284*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x100b1
285*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x100b1
286*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x100b1
287*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x100b1
288*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x100b1
289*4882a593Smuzhiyun			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x100b1
290*4882a593Smuzhiyun		>;
291*4882a593Smuzhiyun	};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun	pinctrl_led: ledgrp {
294*4882a593Smuzhiyun		fsl,pins = <
295*4882a593Smuzhiyun			MX6UL_PAD_LCD_RESET__GPIO3_IO04		0x0b0b0
296*4882a593Smuzhiyun		>;
297*4882a593Smuzhiyun	};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun	pinctrl_pwm3: pwm3grp {
300*4882a593Smuzhiyun		fsl,pins = <
301*4882a593Smuzhiyun			MX6UL_PAD_NAND_ALE__PWM3_OUT		0x1b0b0
302*4882a593Smuzhiyun		>;
303*4882a593Smuzhiyun	};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun	pinctrl_tsc: tscgrp {
306*4882a593Smuzhiyun		fsl,pins = <
307*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01       0xb0
308*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02       0xb0
309*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03       0xb0
310*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04       0xb0
311*4882a593Smuzhiyun		>;
312*4882a593Smuzhiyun	};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun	pinctrl_uart1: uart1grp {
315*4882a593Smuzhiyun		fsl,pins = <
316*4882a593Smuzhiyun			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
317*4882a593Smuzhiyun			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
318*4882a593Smuzhiyun		>;
319*4882a593Smuzhiyun	};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
322*4882a593Smuzhiyun		fsl,pins = <
323*4882a593Smuzhiyun			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
324*4882a593Smuzhiyun			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
325*4882a593Smuzhiyun		>;
326*4882a593Smuzhiyun	};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun	pinctrl_usbotg1_id: usbotg1idgrp {
329*4882a593Smuzhiyun		fsl,pins = <
330*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x1b0b0
331*4882a593Smuzhiyun		>;
332*4882a593Smuzhiyun	};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun	pinctrl_usbotg1_vbus: usbotg1vbusgrp {
335*4882a593Smuzhiyun		fsl,pins = <
336*4882a593Smuzhiyun			MX6UL_PAD_GPIO1_IO05__GPIO1_IO05	0x1b0b0
337*4882a593Smuzhiyun		>;
338*4882a593Smuzhiyun	};
339*4882a593Smuzhiyun};
340