1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright (C) 2014 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "imx6sx.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Freescale i.MX6 SoloX Sabre Auto Board"; 11*4882a593Smuzhiyun compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun memory@80000000 { 14*4882a593Smuzhiyun device_type = "memory"; 15*4882a593Smuzhiyun reg = <0x80000000 0x80000000>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun leds { 19*4882a593Smuzhiyun compatible = "gpio-leds"; 20*4882a593Smuzhiyun pinctrl-names = "default"; 21*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_led>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun user { 24*4882a593Smuzhiyun label = "debug"; 25*4882a593Smuzhiyun gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 26*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun vcc_sd3: regulator-vcc-sd3 { 31*4882a593Smuzhiyun compatible = "regulator-fixed"; 32*4882a593Smuzhiyun pinctrl-names = "default"; 33*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_vcc_sd3>; 34*4882a593Smuzhiyun regulator-name = "VCC_SD3"; 35*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 36*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 37*4882a593Smuzhiyun gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 38*4882a593Smuzhiyun enable-active-high; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun reg_can_wake: regulator-can-wake { 42*4882a593Smuzhiyun compatible = "regulator-fixed"; 43*4882a593Smuzhiyun regulator-name = "can-wake"; 44*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 45*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 46*4882a593Smuzhiyun gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; 47*4882a593Smuzhiyun enable-active-high; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun reg_can_en: regulator-can-en { 51*4882a593Smuzhiyun compatible = "regulator-fixed"; 52*4882a593Smuzhiyun regulator-name = "can-en"; 53*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 54*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 55*4882a593Smuzhiyun gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; 56*4882a593Smuzhiyun enable-active-high; 57*4882a593Smuzhiyun vin-supply = <®_can_wake>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun reg_can_stby: regulator-can-stby { 61*4882a593Smuzhiyun compatible = "regulator-fixed"; 62*4882a593Smuzhiyun regulator-name = "can-stby"; 63*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 64*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 65*4882a593Smuzhiyun gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; 66*4882a593Smuzhiyun enable-active-high; 67*4882a593Smuzhiyun vin-supply = <®_can_en>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun reg_cs42888: cs42888_supply { 71*4882a593Smuzhiyun compatible = "regulator-fixed"; 72*4882a593Smuzhiyun regulator-name = "cs42888_supply"; 73*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 74*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 75*4882a593Smuzhiyun regulator-always-on; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun sound-cs42888 { 79*4882a593Smuzhiyun compatible = "fsl,imx6-sabreauto-cs42888", 80*4882a593Smuzhiyun "fsl,imx-audio-cs42888"; 81*4882a593Smuzhiyun model = "imx-cs42888"; 82*4882a593Smuzhiyun audio-cpu = <&esai>; 83*4882a593Smuzhiyun audio-asrc = <&asrc>; 84*4882a593Smuzhiyun audio-codec = <&cs42888>; 85*4882a593Smuzhiyun audio-routing = 86*4882a593Smuzhiyun "Line Out Jack", "AOUT1L", 87*4882a593Smuzhiyun "Line Out Jack", "AOUT1R", 88*4882a593Smuzhiyun "Line Out Jack", "AOUT2L", 89*4882a593Smuzhiyun "Line Out Jack", "AOUT2R", 90*4882a593Smuzhiyun "Line Out Jack", "AOUT3L", 91*4882a593Smuzhiyun "Line Out Jack", "AOUT3R", 92*4882a593Smuzhiyun "Line Out Jack", "AOUT4L", 93*4882a593Smuzhiyun "Line Out Jack", "AOUT4R", 94*4882a593Smuzhiyun "AIN1L", "Line In Jack", 95*4882a593Smuzhiyun "AIN1R", "Line In Jack", 96*4882a593Smuzhiyun "AIN2L", "Line In Jack", 97*4882a593Smuzhiyun "AIN2R", "Line In Jack"; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun sound-spdif { 101*4882a593Smuzhiyun compatible = "fsl,imx-audio-spdif"; 102*4882a593Smuzhiyun model = "imx-spdif"; 103*4882a593Smuzhiyun spdif-controller = <&spdif>; 104*4882a593Smuzhiyun spdif-in; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun}; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun&anaclk2 { 109*4882a593Smuzhiyun clock-frequency = <24576000>; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&clks { 113*4882a593Smuzhiyun assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, 114*4882a593Smuzhiyun <&clks IMX6SX_PLL4_BYPASS>, 115*4882a593Smuzhiyun <&clks IMX6SX_CLK_PLL4_POST_DIV>; 116*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, 117*4882a593Smuzhiyun <&clks IMX6SX_PLL4_BYPASS_SRC>; 118*4882a593Smuzhiyun assigned-clock-rates = <0>, <0>, <24576000>; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&esai { 122*4882a593Smuzhiyun pinctrl-names = "default"; 123*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_esai>; 124*4882a593Smuzhiyun assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, 125*4882a593Smuzhiyun <&clks IMX6SX_CLK_ESAI_EXTAL>; 126*4882a593Smuzhiyun assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; 127*4882a593Smuzhiyun assigned-clock-rates = <0>, <24576000>; 128*4882a593Smuzhiyun status = "okay"; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&fec1 { 132*4882a593Smuzhiyun pinctrl-names = "default"; 133*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet1>; 134*4882a593Smuzhiyun phy-mode = "rgmii-id"; 135*4882a593Smuzhiyun phy-handle = <ðphy1>; 136*4882a593Smuzhiyun fsl,magic-packet; 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun mdio { 140*4882a593Smuzhiyun #address-cells = <1>; 141*4882a593Smuzhiyun #size-cells = <0>; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 144*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 145*4882a593Smuzhiyun reg = <0>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun ethphy1: ethernet-phy@1 { 149*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 150*4882a593Smuzhiyun reg = <1>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun}; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun&fec2 { 156*4882a593Smuzhiyun pinctrl-names = "default"; 157*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet2>; 158*4882a593Smuzhiyun phy-mode = "rgmii-id"; 159*4882a593Smuzhiyun phy-handle = <ðphy0>; 160*4882a593Smuzhiyun fsl,magic-packet; 161*4882a593Smuzhiyun status = "okay"; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&flexcan1 { 165*4882a593Smuzhiyun pinctrl-names = "default"; 166*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_flexcan1>; 167*4882a593Smuzhiyun xceiver-supply = <®_can_stby>; 168*4882a593Smuzhiyun status = "okay"; 169*4882a593Smuzhiyun}; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun&flexcan2 { 172*4882a593Smuzhiyun pinctrl-names = "default"; 173*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_flexcan2>; 174*4882a593Smuzhiyun xceiver-supply = <®_can_stby>; 175*4882a593Smuzhiyun status = "okay"; 176*4882a593Smuzhiyun}; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun&uart1 { 179*4882a593Smuzhiyun pinctrl-names = "default"; 180*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 181*4882a593Smuzhiyun status = "okay"; 182*4882a593Smuzhiyun}; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun&usdhc3 { 185*4882a593Smuzhiyun pinctrl-names = "default", "state_100mhz", "state_200mhz"; 186*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc3>; 187*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 188*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 189*4882a593Smuzhiyun bus-width = <8>; 190*4882a593Smuzhiyun cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; 191*4882a593Smuzhiyun wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 192*4882a593Smuzhiyun keep-power-in-suspend; 193*4882a593Smuzhiyun wakeup-source; 194*4882a593Smuzhiyun vmmc-supply = <&vcc_sd3>; 195*4882a593Smuzhiyun status = "okay"; 196*4882a593Smuzhiyun}; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun&usdhc4 { 199*4882a593Smuzhiyun pinctrl-names = "default"; 200*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc4>; 201*4882a593Smuzhiyun bus-width = <8>; 202*4882a593Smuzhiyun cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; 203*4882a593Smuzhiyun no-1-8-v; 204*4882a593Smuzhiyun keep-power-in-suspend; 205*4882a593Smuzhiyun wakeup-source; 206*4882a593Smuzhiyun status = "okay"; 207*4882a593Smuzhiyun}; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun&iomuxc { 210*4882a593Smuzhiyun pinctrl_egalax_int: egalax-intgrp { 211*4882a593Smuzhiyun fsl,pins = < 212*4882a593Smuzhiyun MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0 213*4882a593Smuzhiyun >; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun pinctrl_enet1: enet1grp { 217*4882a593Smuzhiyun fsl,pins = < 218*4882a593Smuzhiyun MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 219*4882a593Smuzhiyun MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 220*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 221*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 222*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 223*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 224*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 225*4882a593Smuzhiyun MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 226*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 227*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 228*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 229*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 230*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 231*4882a593Smuzhiyun MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 232*4882a593Smuzhiyun >; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun pinctrl_enet2: enet2grp { 236*4882a593Smuzhiyun fsl,pins = < 237*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 238*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 239*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 240*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 241*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 242*4882a593Smuzhiyun MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 243*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 244*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 245*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 246*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 247*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 248*4882a593Smuzhiyun MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 249*4882a593Smuzhiyun >; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun pinctrl_esai: esaigrp { 253*4882a593Smuzhiyun fsl,pins = < 254*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 255*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 256*4882a593Smuzhiyun MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 257*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 258*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 259*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 260*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 261*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 262*4882a593Smuzhiyun MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 263*4882a593Smuzhiyun MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 264*4882a593Smuzhiyun >; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun pinctrl_flexcan1: flexcan1grp { 268*4882a593Smuzhiyun fsl,pins = < 269*4882a593Smuzhiyun MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 270*4882a593Smuzhiyun MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 271*4882a593Smuzhiyun >; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun pinctrl_flexcan2: flexcan2grp { 275*4882a593Smuzhiyun fsl,pins = < 276*4882a593Smuzhiyun MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 277*4882a593Smuzhiyun MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 278*4882a593Smuzhiyun >; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 282*4882a593Smuzhiyun fsl,pins = < 283*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 284*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 285*4882a593Smuzhiyun >; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 289*4882a593Smuzhiyun fsl,pins = < 290*4882a593Smuzhiyun MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 291*4882a593Smuzhiyun MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 292*4882a593Smuzhiyun >; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun pinctrl_led: ledgrp { 296*4882a593Smuzhiyun fsl,pins = < 297*4882a593Smuzhiyun MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059 298*4882a593Smuzhiyun >; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun pinctrl_spdif: spdifgrp { 302*4882a593Smuzhiyun fsl,pins = < 303*4882a593Smuzhiyun MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 304*4882a593Smuzhiyun >; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 308*4882a593Smuzhiyun fsl,pins = < 309*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 310*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 311*4882a593Smuzhiyun >; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun pinctrl_usdhc3: usdhc3grp { 315*4882a593Smuzhiyun fsl,pins = < 316*4882a593Smuzhiyun MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 317*4882a593Smuzhiyun MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 318*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 319*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 320*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 321*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 322*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 323*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 324*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 325*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 326*4882a593Smuzhiyun MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ 327*4882a593Smuzhiyun MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ 328*4882a593Smuzhiyun >; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { 332*4882a593Smuzhiyun fsl,pins = < 333*4882a593Smuzhiyun MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 334*4882a593Smuzhiyun MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 335*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 336*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 337*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 338*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 339*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 340*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 341*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 342*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 343*4882a593Smuzhiyun >; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { 347*4882a593Smuzhiyun fsl,pins = < 348*4882a593Smuzhiyun MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 349*4882a593Smuzhiyun MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 350*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 351*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 352*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 353*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 354*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 355*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 356*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 357*4882a593Smuzhiyun MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 358*4882a593Smuzhiyun >; 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun pinctrl_usdhc4: usdhc4grp { 362*4882a593Smuzhiyun fsl,pins = < 363*4882a593Smuzhiyun MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 364*4882a593Smuzhiyun MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 365*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 366*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 367*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 368*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 369*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ 370*4882a593Smuzhiyun MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ 371*4882a593Smuzhiyun >; 372*4882a593Smuzhiyun }; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun pinctrl_vcc_sd3: vccsd3grp { 375*4882a593Smuzhiyun fsl,pins = < 376*4882a593Smuzhiyun MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 377*4882a593Smuzhiyun >; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 381*4882a593Smuzhiyun fsl,pins = < 382*4882a593Smuzhiyun MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 383*4882a593Smuzhiyun >; 384*4882a593Smuzhiyun }; 385*4882a593Smuzhiyun}; 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun&i2c2 { 388*4882a593Smuzhiyun clock-frequency = <100000>; 389*4882a593Smuzhiyun pinctrl-names = "default"; 390*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 391*4882a593Smuzhiyun status = "okay"; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun cs42888: cs42888@48 { 394*4882a593Smuzhiyun compatible = "cirrus,cs42888"; 395*4882a593Smuzhiyun reg = <0x48>; 396*4882a593Smuzhiyun clocks = <&anaclk2 0>; 397*4882a593Smuzhiyun clock-names = "mclk"; 398*4882a593Smuzhiyun VA-supply = <®_cs42888>; 399*4882a593Smuzhiyun VD-supply = <®_cs42888>; 400*4882a593Smuzhiyun VLS-supply = <®_cs42888>; 401*4882a593Smuzhiyun VLC-supply = <®_cs42888>; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun touchscreen@4 { 405*4882a593Smuzhiyun compatible = "eeti,egalax_ts"; 406*4882a593Smuzhiyun reg = <0x04>; 407*4882a593Smuzhiyun pinctrl-names = "default"; 408*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_egalax_int>; 409*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 410*4882a593Smuzhiyun interrupts = <22 IRQ_TYPE_EDGE_FALLING>; 411*4882a593Smuzhiyun wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun pfuze100: pmic@8 { 415*4882a593Smuzhiyun compatible = "fsl,pfuze100"; 416*4882a593Smuzhiyun reg = <0x08>; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun regulators { 419*4882a593Smuzhiyun sw1a_reg: sw1ab { 420*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 421*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 422*4882a593Smuzhiyun regulator-boot-on; 423*4882a593Smuzhiyun regulator-always-on; 424*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun sw1c_reg: sw1c { 428*4882a593Smuzhiyun regulator-min-microvolt = <300000>; 429*4882a593Smuzhiyun regulator-max-microvolt = <1875000>; 430*4882a593Smuzhiyun regulator-boot-on; 431*4882a593Smuzhiyun regulator-always-on; 432*4882a593Smuzhiyun regulator-ramp-delay = <6250>; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun sw2_reg: sw2 { 436*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 437*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 438*4882a593Smuzhiyun regulator-boot-on; 439*4882a593Smuzhiyun regulator-always-on; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun sw3a_reg: sw3a { 443*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 444*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 445*4882a593Smuzhiyun regulator-boot-on; 446*4882a593Smuzhiyun regulator-always-on; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun sw3b_reg: sw3b { 450*4882a593Smuzhiyun regulator-min-microvolt = <400000>; 451*4882a593Smuzhiyun regulator-max-microvolt = <1975000>; 452*4882a593Smuzhiyun regulator-boot-on; 453*4882a593Smuzhiyun regulator-always-on; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun sw4_reg: sw4 { 457*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 458*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 459*4882a593Smuzhiyun regulator-always-on; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun swbst_reg: swbst { 463*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 464*4882a593Smuzhiyun regulator-max-microvolt = <5150000>; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun snvs_reg: vsnvs { 468*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 469*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 470*4882a593Smuzhiyun regulator-boot-on; 471*4882a593Smuzhiyun regulator-always-on; 472*4882a593Smuzhiyun }; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun vref_reg: vrefddr { 475*4882a593Smuzhiyun regulator-boot-on; 476*4882a593Smuzhiyun regulator-always-on; 477*4882a593Smuzhiyun }; 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun vgen1_reg: vgen1 { 480*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 481*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 482*4882a593Smuzhiyun regulator-always-on; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun vgen2_reg: vgen2 { 486*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 487*4882a593Smuzhiyun regulator-max-microvolt = <1550000>; 488*4882a593Smuzhiyun }; 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun vgen3_reg: vgen3 { 491*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 492*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 493*4882a593Smuzhiyun regulator-always-on; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun vgen4_reg: vgen4 { 497*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 498*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 499*4882a593Smuzhiyun regulator-always-on; 500*4882a593Smuzhiyun }; 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun vgen5_reg: vgen5 { 503*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 504*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 505*4882a593Smuzhiyun regulator-always-on; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun vgen6_reg: vgen6 { 509*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 510*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 511*4882a593Smuzhiyun regulator-always-on; 512*4882a593Smuzhiyun }; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun max7322: gpio@68 { 517*4882a593Smuzhiyun compatible = "maxim,max7322"; 518*4882a593Smuzhiyun reg = <0x68>; 519*4882a593Smuzhiyun gpio-controller; 520*4882a593Smuzhiyun #gpio-cells = <2>; 521*4882a593Smuzhiyun }; 522*4882a593Smuzhiyun}; 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun&i2c3 { 525*4882a593Smuzhiyun clock-frequency = <100000>; 526*4882a593Smuzhiyun pinctrl-names = "default"; 527*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 528*4882a593Smuzhiyun status = "okay"; 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun max7310_a: gpio@30 { 531*4882a593Smuzhiyun compatible = "maxim,max7310"; 532*4882a593Smuzhiyun reg = <0x30>; 533*4882a593Smuzhiyun gpio-controller; 534*4882a593Smuzhiyun #gpio-cells = <2>; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun max7310_b: gpio@32 { 538*4882a593Smuzhiyun compatible = "maxim,max7310"; 539*4882a593Smuzhiyun reg = <0x32>; 540*4882a593Smuzhiyun gpio-controller; 541*4882a593Smuzhiyun #gpio-cells = <2>; 542*4882a593Smuzhiyun }; 543*4882a593Smuzhiyun}; 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun&spdif { 546*4882a593Smuzhiyun pinctrl-names = "default"; 547*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_spdif>; 548*4882a593Smuzhiyun assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>; 549*4882a593Smuzhiyun assigned-clock-rates = <24576000>; 550*4882a593Smuzhiyun status = "okay"; 551*4882a593Smuzhiyun}; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun&wdog1 { 554*4882a593Smuzhiyun pinctrl-names = "default"; 555*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 556*4882a593Smuzhiyun fsl,ext-reset-output; 557*4882a593Smuzhiyun}; 558