1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ OR MIT 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2016 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "imx6qp.dtsi" 8*4882a593Smuzhiyun#include "imx6qdl-sabreauto.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; 12*4882a593Smuzhiyun compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; 13*4882a593Smuzhiyun}; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun&i2c2 { 16*4882a593Smuzhiyun max7322: gpio@68 { 17*4882a593Smuzhiyun compatible = "maxim,max7322"; 18*4882a593Smuzhiyun reg = <0x68>; 19*4882a593Smuzhiyun gpio-controller; 20*4882a593Smuzhiyun #gpio-cells = <2>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun}; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun&iomuxc { 25*4882a593Smuzhiyun imx6qdl-sabreauto { 26*4882a593Smuzhiyun pinctrl_enet: enetgrp { 27*4882a593Smuzhiyun fsl,pins = < 28*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 29*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 30*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 31*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 32*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 33*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 34*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 35*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 36*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 37*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 38*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 39*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 40*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 41*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 42*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 43*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 44*4882a593Smuzhiyun >; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&pcie { 50*4882a593Smuzhiyun reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&sata { 55*4882a593Smuzhiyun status = "okay"; 56*4882a593Smuzhiyun}; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun&vgen3_reg { 59*4882a593Smuzhiyun regulator-always-on; 60*4882a593Smuzhiyun}; 61