xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/imx6qdl-var-dart.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Support for Variscite DART-MX6 Module
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2017 BayLibre, SAS
6*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/sound/fsl-imx-audmux.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	memory@10000000 {
14*4882a593Smuzhiyun		device_type = "memory";
15*4882a593Smuzhiyun		reg = <0x10000000 0x40000000>;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	reg_3p3v: regulator-3p3v {
19*4882a593Smuzhiyun		compatible = "regulator-fixed";
20*4882a593Smuzhiyun		regulator-name = "3P3V";
21*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
22*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
23*4882a593Smuzhiyun		regulator-always-on;
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	reg_wl18xx_vmmc: regulator-wl18xx {
27*4882a593Smuzhiyun		compatible = "regulator-fixed";
28*4882a593Smuzhiyun		regulator-name = "vwl1807";
29*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
30*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
31*4882a593Smuzhiyun		gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
32*4882a593Smuzhiyun		enable-active-high;
33*4882a593Smuzhiyun		startup-delay-us = <70000>;
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun&audmux {
38*4882a593Smuzhiyun	pinctrl-names = "default";
39*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
40*4882a593Smuzhiyun	status = "okay";
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	ssi2 {
43*4882a593Smuzhiyun		fsl,audmux-port = <1>;
44*4882a593Smuzhiyun		fsl,port-config = <
45*4882a593Smuzhiyun			(IMX_AUDMUX_V2_PTCR_SYN |
46*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TFSDIR |
47*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TFSEL(2) |
48*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TCLKDIR |
49*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_TCSEL(2))
50*4882a593Smuzhiyun			IMX_AUDMUX_V2_PDCR_RXDSEL(2)
51*4882a593Smuzhiyun		>;
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	aud3 {
55*4882a593Smuzhiyun		fsl,audmux-port = <2>;
56*4882a593Smuzhiyun		fsl,port-config = <
57*4882a593Smuzhiyun			IMX_AUDMUX_V2_PTCR_SYN
58*4882a593Smuzhiyun			IMX_AUDMUX_V2_PDCR_RXDSEL(1)
59*4882a593Smuzhiyun		>;
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun&can1 {
64*4882a593Smuzhiyun	pinctrl-names = "default";
65*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
66*4882a593Smuzhiyun	status = "disabled";
67*4882a593Smuzhiyun};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun&can2 {
70*4882a593Smuzhiyun	pinctrl-names = "default";
71*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
72*4882a593Smuzhiyun	status = "disabled";
73*4882a593Smuzhiyun};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun&ecspi1 {
76*4882a593Smuzhiyun	pinctrl-names = "default";
77*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
78*4882a593Smuzhiyun	status = "disabled";
79*4882a593Smuzhiyun};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun&fec {
82*4882a593Smuzhiyun	pinctrl-names = "default";
83*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
84*4882a593Smuzhiyun	phy-mode = "rgmii";
85*4882a593Smuzhiyun	status = "disabled";
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&hdmi {
89*4882a593Smuzhiyun	pinctrl-names = "default";
90*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hdmicec>;
91*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c1>;
92*4882a593Smuzhiyun	status = "disabled";
93*4882a593Smuzhiyun};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun&i2c1 {
96*4882a593Smuzhiyun	pinctrl-names = "default";
97*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
98*4882a593Smuzhiyun	status = "disabled";
99*4882a593Smuzhiyun};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun&i2c2 {
102*4882a593Smuzhiyun	clock-frequency = <100000>;
103*4882a593Smuzhiyun	pinctrl-names = "default";
104*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
105*4882a593Smuzhiyun	status = "okay";
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun	pmic@8 {
108*4882a593Smuzhiyun		pinctrl-names = "default";
109*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_pmic>;
110*4882a593Smuzhiyun		compatible = "fsl,pfuze100";
111*4882a593Smuzhiyun		reg = <0x08>;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun		regulators {
114*4882a593Smuzhiyun			sw1a_reg: sw1ab {
115*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
116*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
117*4882a593Smuzhiyun				regulator-boot-on;
118*4882a593Smuzhiyun				regulator-always-on;
119*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
120*4882a593Smuzhiyun			};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun			sw1c_reg: sw1c {
123*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
124*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
125*4882a593Smuzhiyun				regulator-boot-on;
126*4882a593Smuzhiyun				regulator-always-on;
127*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
128*4882a593Smuzhiyun			};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun			sw2_reg: sw2 {
131*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
132*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
133*4882a593Smuzhiyun				regulator-boot-on;
134*4882a593Smuzhiyun				regulator-always-on;
135*4882a593Smuzhiyun			};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun			sw3a_reg: sw3a {
138*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
139*4882a593Smuzhiyun				regulator-max-microvolt = <3950000>;
140*4882a593Smuzhiyun				regulator-boot-on;
141*4882a593Smuzhiyun				regulator-always-on;
142*4882a593Smuzhiyun			};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun			sw3b_reg: sw3b {
145*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
146*4882a593Smuzhiyun				regulator-max-microvolt = <3950000>;
147*4882a593Smuzhiyun				regulator-boot-on;
148*4882a593Smuzhiyun				regulator-always-on;
149*4882a593Smuzhiyun			};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun			sw4_reg: sw4 {
152*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
153*4882a593Smuzhiyun				regulator-max-microvolt = <3950000>;
154*4882a593Smuzhiyun			};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun			snvs_reg: vsnvs {
157*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
158*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
159*4882a593Smuzhiyun				regulator-boot-on;
160*4882a593Smuzhiyun				regulator-always-on;
161*4882a593Smuzhiyun			};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			vref_reg: vrefddr {
164*4882a593Smuzhiyun				regulator-boot-on;
165*4882a593Smuzhiyun				regulator-always-on;
166*4882a593Smuzhiyun			};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun			vgen6_reg: vgen6 {
169*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
170*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
171*4882a593Smuzhiyun				regulator-always-on;
172*4882a593Smuzhiyun				regulator-boot-on;
173*4882a593Smuzhiyun			};
174*4882a593Smuzhiyun		};
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	tlv320aic3106: codec@1b {
178*4882a593Smuzhiyun		compatible = "ti,tlv320aic3106";
179*4882a593Smuzhiyun		reg = <0x1b>;
180*4882a593Smuzhiyun		#sound-dai-cells = <0>;
181*4882a593Smuzhiyun		DRVDD-supply = <&reg_3p3v>;
182*4882a593Smuzhiyun		AVDD-supply = <&reg_3p3v>;
183*4882a593Smuzhiyun		IOVDD-supply = <&reg_3p3v>;
184*4882a593Smuzhiyun		DVDD-supply = <&reg_3p3v>;
185*4882a593Smuzhiyun		ai3x-ocmv = <0>;
186*4882a593Smuzhiyun		reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun&i2c3 {
191*4882a593Smuzhiyun	pinctrl-names = "default";
192*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
193*4882a593Smuzhiyun	status = "disabled";
194*4882a593Smuzhiyun};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun&iomuxc {
197*4882a593Smuzhiyun	pinctrl_audmux: audmux {
198*4882a593Smuzhiyun		fsl,pins = <
199*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
200*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
201*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
202*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
203*4882a593Smuzhiyun			/* Audio Clock */
204*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0
205*4882a593Smuzhiyun		>;
206*4882a593Smuzhiyun	};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun	pinctrl_bt: bt {
209*4882a593Smuzhiyun		fsl,pins = <
210*4882a593Smuzhiyun			/* Bluetooth enable */
211*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT6__GPIO6_IO18		0x1b0b1
212*4882a593Smuzhiyun			/* Bluetooth Slow Clock */
213*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT	0x000b0
214*4882a593Smuzhiyun		>;
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun	pinctrl_ecspi1: ecspi1grp {
218*4882a593Smuzhiyun		fsl,pins = <
219*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
220*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
221*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
222*4882a593Smuzhiyun			/* SPI1 CS0 */
223*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
224*4882a593Smuzhiyun			/* SPI1 CS1 */
225*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL2__GPIO4_IO10		0x1b0b0
226*4882a593Smuzhiyun		>;
227*4882a593Smuzhiyun	};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun	pinctrl_enet: enetgrp {
230*4882a593Smuzhiyun		fsl,pins = <
231*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
232*4882a593Smuzhiyun			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
233*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
234*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
235*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
236*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
237*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
238*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
239*4882a593Smuzhiyun			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
240*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
241*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
242*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
243*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
244*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
245*4882a593Smuzhiyun			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
246*4882a593Smuzhiyun		>;
247*4882a593Smuzhiyun	};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun	pinctrl_flexcan1: flexcan1grp {
250*4882a593Smuzhiyun		fsl,pins = <
251*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX	0x1b0b0
252*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX	0x1b0b0
253*4882a593Smuzhiyun		>;
254*4882a593Smuzhiyun	};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun	pinctrl_flexcan2: flexcan2grp {
257*4882a593Smuzhiyun		fsl,pins = <
258*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b0b0
259*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b0b0
260*4882a593Smuzhiyun		>;
261*4882a593Smuzhiyun	};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun	pinctrl_hdmicec: hdmicecgrp {
264*4882a593Smuzhiyun		fsl,pins = <
265*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
266*4882a593Smuzhiyun		>;
267*4882a593Smuzhiyun	};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
270*4882a593Smuzhiyun		fsl,pins = <
271*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA	0x4001b8b1
272*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL	0x4001b8b1
273*4882a593Smuzhiyun		>;
274*4882a593Smuzhiyun	};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
277*4882a593Smuzhiyun		fsl,pins = <
278*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__I2C2_SCL	0x4001b8b1
279*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
280*4882a593Smuzhiyun		>;
281*4882a593Smuzhiyun	};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun	pinctrl_i2c3: i2c3grp {
284*4882a593Smuzhiyun		fsl,pins = <
285*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_5__I2C3_SCL	0x4001b8b1
286*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_16__I2C3_SDA	0x4001b8b1
287*4882a593Smuzhiyun		>;
288*4882a593Smuzhiyun	};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun	pinctrl_pmic: pmicgrp {
291*4882a593Smuzhiyun		fsl,pins = <
292*4882a593Smuzhiyun			/* PMIC INT */
293*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b1
294*4882a593Smuzhiyun		>;
295*4882a593Smuzhiyun	};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun	pinctrl_pwm2: pwm2grp {
298*4882a593Smuzhiyun		fsl,pins = <
299*4882a593Smuzhiyun			MX6QDL_PAD_DISP0_DAT9__PWM2_OUT	0x1b0b1
300*4882a593Smuzhiyun		>;
301*4882a593Smuzhiyun	};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun	pinctrl_uart1: uart1grp {
304*4882a593Smuzhiyun		fsl,pins = <
305*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
306*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
307*4882a593Smuzhiyun		>;
308*4882a593Smuzhiyun	};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
311*4882a593Smuzhiyun		fsl,pins = <
312*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA	0x1b0b1
313*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA	0x1b0b1
314*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT6__UART2_CTS_B	0x1b0b1
315*4882a593Smuzhiyun			MX6QDL_PAD_SD4_DAT5__UART2_RTS_B	0x1b0b1
316*4882a593Smuzhiyun		>;
317*4882a593Smuzhiyun	};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
320*4882a593Smuzhiyun		fsl,pins = <
321*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
322*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
323*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b1
324*4882a593Smuzhiyun			MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
325*4882a593Smuzhiyun		>;
326*4882a593Smuzhiyun	};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun	pinctrl_usbotg: usbotggrp {
329*4882a593Smuzhiyun		fsl,pins = <
330*4882a593Smuzhiyun			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
331*4882a593Smuzhiyun		>;
332*4882a593Smuzhiyun	};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
335*4882a593Smuzhiyun		fsl,pins = <
336*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17059
337*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10059
338*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17059
339*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17059
340*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17059
341*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17059
342*4882a593Smuzhiyun			/* WL_EN */
343*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071
344*4882a593Smuzhiyun			/* WL_IRQ */
345*4882a593Smuzhiyun			MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x17071
346*4882a593Smuzhiyun		>;
347*4882a593Smuzhiyun	};
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
350*4882a593Smuzhiyun		fsl,pins = <
351*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x170B9
352*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x100B9
353*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x170B9
354*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x170B9
355*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x170B9
356*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x170B9
357*4882a593Smuzhiyun		>;
358*4882a593Smuzhiyun	};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
361*4882a593Smuzhiyun		fsl,pins = <
362*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x170F9
363*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x100F9
364*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x170F9
365*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x170F9
366*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x170F9
367*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x170F9
368*4882a593Smuzhiyun		>;
369*4882a593Smuzhiyun	};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
372*4882a593Smuzhiyun		fsl,pins = <
373*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CMD__SD2_CMD	0x17059
374*4882a593Smuzhiyun			MX6QDL_PAD_SD2_CLK__SD2_CLK	0x10059
375*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT0__SD2_DATA0	0x17059
376*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT1__SD2_DATA1	0x17059
377*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT2__SD2_DATA2	0x17059
378*4882a593Smuzhiyun			MX6QDL_PAD_SD2_DAT3__SD2_DATA3	0x17059
379*4882a593Smuzhiyun		>;
380*4882a593Smuzhiyun	};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun	pinctrl_usdhc3: usdhc3grp {
383*4882a593Smuzhiyun		fsl,pins = <
384*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
385*4882a593Smuzhiyun			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
386*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
387*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
388*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
389*4882a593Smuzhiyun			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
390*4882a593Smuzhiyun		>;
391*4882a593Smuzhiyun	};
392*4882a593Smuzhiyun};
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun&pcie {
395*4882a593Smuzhiyun	fsl,tx-swing-full = <103>;
396*4882a593Smuzhiyun	fsl,tx-swing-low = <103>;
397*4882a593Smuzhiyun	reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
398*4882a593Smuzhiyun	status = "disabled";
399*4882a593Smuzhiyun};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun&pwm2 {
402*4882a593Smuzhiyun	pinctrl-names = "default";
403*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm2>;
404*4882a593Smuzhiyun	status = "disabled";
405*4882a593Smuzhiyun};
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun&reg_arm {
408*4882a593Smuzhiyun	vin-supply = <&sw1a_reg>;
409*4882a593Smuzhiyun};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun&reg_pu {
412*4882a593Smuzhiyun	vin-supply = <&sw1c_reg>;
413*4882a593Smuzhiyun};
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun&reg_soc {
416*4882a593Smuzhiyun	vin-supply = <&sw1c_reg>;
417*4882a593Smuzhiyun};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun&snvs_poweroff {
420*4882a593Smuzhiyun	status = "okay";
421*4882a593Smuzhiyun};
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun&ssi2 {
424*4882a593Smuzhiyun	status = "okay";
425*4882a593Smuzhiyun};
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun&uart1 {
428*4882a593Smuzhiyun	pinctrl-names = "default";
429*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
430*4882a593Smuzhiyun	status = "disabled";
431*4882a593Smuzhiyun};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun&uart2 {
434*4882a593Smuzhiyun	pinctrl-names = "default";
435*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>;
436*4882a593Smuzhiyun	uart-has-rtscts;
437*4882a593Smuzhiyun	status = "okay";
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun	bluetooth {
440*4882a593Smuzhiyun		compatible = "ti,wl1835-st";
441*4882a593Smuzhiyun		enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>;
442*4882a593Smuzhiyun	};
443*4882a593Smuzhiyun};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun&uart3 {
446*4882a593Smuzhiyun	pinctrl-names = "default";
447*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
448*4882a593Smuzhiyun	uart-has-rtscts;
449*4882a593Smuzhiyun	status = "disabled";
450*4882a593Smuzhiyun};
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun&usbh1 {
453*4882a593Smuzhiyun	status = "disabled";
454*4882a593Smuzhiyun};
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun&usbotg {
457*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
458*4882a593Smuzhiyun	pinctrl-names = "default";
459*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
460*4882a593Smuzhiyun	disable-over-current;
461*4882a593Smuzhiyun	status = "disabled";
462*4882a593Smuzhiyun};
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun&usdhc1 {
465*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
466*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
467*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
468*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
469*4882a593Smuzhiyun	bus-width = <4>;
470*4882a593Smuzhiyun	vmmc-supply = <&reg_wl18xx_vmmc>;
471*4882a593Smuzhiyun	non-removable;
472*4882a593Smuzhiyun	wakeup-source;
473*4882a593Smuzhiyun	keep-power-in-suspend;
474*4882a593Smuzhiyun	cap-power-off-card;
475*4882a593Smuzhiyun	#address-cells = <1>;
476*4882a593Smuzhiyun	#size-cells = <0>;
477*4882a593Smuzhiyun	status = "okay";
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun	wlcore: wlcore@2 {
480*4882a593Smuzhiyun		compatible = "ti,wl1835";
481*4882a593Smuzhiyun		reg = <2>;
482*4882a593Smuzhiyun		interrupt-parent = <&gpio6>;
483*4882a593Smuzhiyun		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
484*4882a593Smuzhiyun		ref-clock-frequency = <38400000>;
485*4882a593Smuzhiyun	};
486*4882a593Smuzhiyun};
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun&usdhc2 {
489*4882a593Smuzhiyun	pinctrl-names = "default";
490*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
491*4882a593Smuzhiyun	no-1-8-v;
492*4882a593Smuzhiyun	keep-power-in-suspend;
493*4882a593Smuzhiyun	wakeup-source;
494*4882a593Smuzhiyun	status = "disabled";
495*4882a593Smuzhiyun};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun&usdhc3 {
498*4882a593Smuzhiyun	pinctrl-names = "default";
499*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
500*4882a593Smuzhiyun	non-removable;
501*4882a593Smuzhiyun	keep-power-in-suspend;
502*4882a593Smuzhiyun	wakeup-source;
503*4882a593Smuzhiyun	status = "okay";
504*4882a593Smuzhiyun};
505