xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/imx6qdl-sabreauto.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2012 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun// Copyright 2011 Linaro Ltd.
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
7*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	chosen {
11*4882a593Smuzhiyun		stdout-path = &uart4;
12*4882a593Smuzhiyun	};
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	memory@10000000 {
15*4882a593Smuzhiyun		device_type = "memory";
16*4882a593Smuzhiyun		reg = <0x10000000 0x80000000>;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	leds {
20*4882a593Smuzhiyun		compatible = "gpio-leds";
21*4882a593Smuzhiyun		pinctrl-names = "default";
22*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_leds>;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun		user {
25*4882a593Smuzhiyun			label = "debug";
26*4882a593Smuzhiyun			gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
27*4882a593Smuzhiyun		};
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	gpio-keys {
31*4882a593Smuzhiyun		compatible = "gpio-keys";
32*4882a593Smuzhiyun		pinctrl-names = "default";
33*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_keys>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		home {
36*4882a593Smuzhiyun			label = "Home";
37*4882a593Smuzhiyun			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
38*4882a593Smuzhiyun			linux,code = <KEY_HOME>;
39*4882a593Smuzhiyun			wakeup-source;
40*4882a593Smuzhiyun		};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun		back {
43*4882a593Smuzhiyun			label = "Back";
44*4882a593Smuzhiyun			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
45*4882a593Smuzhiyun			linux,code = <KEY_BACK>;
46*4882a593Smuzhiyun			wakeup-source;
47*4882a593Smuzhiyun		};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun		program {
50*4882a593Smuzhiyun			label = "Program";
51*4882a593Smuzhiyun			gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
52*4882a593Smuzhiyun			linux,code = <KEY_PROGRAM>;
53*4882a593Smuzhiyun			wakeup-source;
54*4882a593Smuzhiyun		};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun		volume-up {
57*4882a593Smuzhiyun			label = "Volume Up";
58*4882a593Smuzhiyun			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
59*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
60*4882a593Smuzhiyun			wakeup-source;
61*4882a593Smuzhiyun		};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		volume-down {
64*4882a593Smuzhiyun			label = "Volume Down";
65*4882a593Smuzhiyun			gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
66*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
67*4882a593Smuzhiyun			wakeup-source;
68*4882a593Smuzhiyun		};
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	clocks {
72*4882a593Smuzhiyun		codec_osc: anaclk2 {
73*4882a593Smuzhiyun			compatible = "fixed-clock";
74*4882a593Smuzhiyun			#clock-cells = <0>;
75*4882a593Smuzhiyun			clock-frequency = <24576000>;
76*4882a593Smuzhiyun		};
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	reg_audio: regulator-audio {
80*4882a593Smuzhiyun		compatible = "regulator-fixed";
81*4882a593Smuzhiyun		regulator-name = "cs42888_supply";
82*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
83*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
84*4882a593Smuzhiyun		regulator-always-on;
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	reg_usb_h1_vbus: regulator-usb-h1-vbus {
88*4882a593Smuzhiyun		compatible = "regulator-fixed";
89*4882a593Smuzhiyun		regulator-name = "usb_h1_vbus";
90*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
91*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
92*4882a593Smuzhiyun		gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
93*4882a593Smuzhiyun		enable-active-high;
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	reg_usb_otg_vbus: regulator-usb-otg-vbus {
97*4882a593Smuzhiyun		compatible = "regulator-fixed";
98*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
99*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
100*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
101*4882a593Smuzhiyun		gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
102*4882a593Smuzhiyun		enable-active-high;
103*4882a593Smuzhiyun	};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun	reg_can_en: regulator-can-en {
106*4882a593Smuzhiyun		compatible = "regulator-fixed";
107*4882a593Smuzhiyun		regulator-name = "can-en";
108*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
109*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
110*4882a593Smuzhiyun		gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
111*4882a593Smuzhiyun		enable-active-high;
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	reg_can_stby: regulator-can-stby {
115*4882a593Smuzhiyun		compatible = "regulator-fixed";
116*4882a593Smuzhiyun		regulator-name = "can-stby";
117*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
118*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
119*4882a593Smuzhiyun		gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
120*4882a593Smuzhiyun		enable-active-high;
121*4882a593Smuzhiyun		vin-supply = <&reg_can_en>;
122*4882a593Smuzhiyun	};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	sound-cs42888 {
125*4882a593Smuzhiyun		compatible = "fsl,imx6-sabreauto-cs42888",
126*4882a593Smuzhiyun			"fsl,imx-audio-cs42888";
127*4882a593Smuzhiyun		model = "imx-cs42888";
128*4882a593Smuzhiyun		audio-cpu = <&esai>;
129*4882a593Smuzhiyun		audio-asrc = <&asrc>;
130*4882a593Smuzhiyun		audio-codec = <&codec>;
131*4882a593Smuzhiyun		audio-routing =
132*4882a593Smuzhiyun			"Line Out Jack", "AOUT1L",
133*4882a593Smuzhiyun			"Line Out Jack", "AOUT1R",
134*4882a593Smuzhiyun			"Line Out Jack", "AOUT2L",
135*4882a593Smuzhiyun			"Line Out Jack", "AOUT2R",
136*4882a593Smuzhiyun			"Line Out Jack", "AOUT3L",
137*4882a593Smuzhiyun			"Line Out Jack", "AOUT3R",
138*4882a593Smuzhiyun			"Line Out Jack", "AOUT4L",
139*4882a593Smuzhiyun			"Line Out Jack", "AOUT4R",
140*4882a593Smuzhiyun			"AIN1L", "Line In Jack",
141*4882a593Smuzhiyun			"AIN1R", "Line In Jack",
142*4882a593Smuzhiyun			"AIN2L", "Line In Jack",
143*4882a593Smuzhiyun			"AIN2R", "Line In Jack";
144*4882a593Smuzhiyun	};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun	sound-spdif {
147*4882a593Smuzhiyun		compatible = "fsl,imx-audio-spdif",
148*4882a593Smuzhiyun			   "fsl,imx-sabreauto-spdif";
149*4882a593Smuzhiyun		model = "imx-spdif";
150*4882a593Smuzhiyun		spdif-controller = <&spdif>;
151*4882a593Smuzhiyun		spdif-in;
152*4882a593Smuzhiyun	};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun	backlight {
155*4882a593Smuzhiyun		compatible = "pwm-backlight";
156*4882a593Smuzhiyun		pwms = <&pwm3 0 5000000>;
157*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
158*4882a593Smuzhiyun		default-brightness-level = <7>;
159*4882a593Smuzhiyun		status = "okay";
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun	i2cmux {
163*4882a593Smuzhiyun		compatible = "i2c-mux-gpio";
164*4882a593Smuzhiyun		#address-cells = <1>;
165*4882a593Smuzhiyun		#size-cells = <0>;
166*4882a593Smuzhiyun		pinctrl-names = "default";
167*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_i2c3mux>;
168*4882a593Smuzhiyun		mux-gpios = <&gpio5 4 0>;
169*4882a593Smuzhiyun		i2c-parent = <&i2c3>;
170*4882a593Smuzhiyun		idle-state = <0>;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun		i2c@1 {
173*4882a593Smuzhiyun			#address-cells = <1>;
174*4882a593Smuzhiyun			#size-cells = <0>;
175*4882a593Smuzhiyun			reg = <1>;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun			adv7180: camera@21 {
178*4882a593Smuzhiyun				compatible = "adi,adv7180";
179*4882a593Smuzhiyun				reg = <0x21>;
180*4882a593Smuzhiyun				powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
181*4882a593Smuzhiyun				interrupt-parent = <&gpio1>;
182*4882a593Smuzhiyun				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun				port {
185*4882a593Smuzhiyun					adv7180_to_ipu1_csi0_mux: endpoint {
186*4882a593Smuzhiyun						remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
187*4882a593Smuzhiyun						bus-width = <8>;
188*4882a593Smuzhiyun					};
189*4882a593Smuzhiyun				};
190*4882a593Smuzhiyun			};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun			max7310_a: gpio@30 {
193*4882a593Smuzhiyun				compatible = "maxim,max7310";
194*4882a593Smuzhiyun				reg = <0x30>;
195*4882a593Smuzhiyun				gpio-controller;
196*4882a593Smuzhiyun				#gpio-cells = <2>;
197*4882a593Smuzhiyun			};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun			max7310_b: gpio@32 {
200*4882a593Smuzhiyun				compatible = "maxim,max7310";
201*4882a593Smuzhiyun				reg = <0x32>;
202*4882a593Smuzhiyun				gpio-controller;
203*4882a593Smuzhiyun				#gpio-cells = <2>;
204*4882a593Smuzhiyun				pinctrl-names = "default";
205*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_max7310>;
206*4882a593Smuzhiyun				reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
207*4882a593Smuzhiyun			};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun			max7310_c: gpio@34 {
210*4882a593Smuzhiyun				compatible = "maxim,max7310";
211*4882a593Smuzhiyun				reg = <0x34>;
212*4882a593Smuzhiyun				gpio-controller;
213*4882a593Smuzhiyun				#gpio-cells = <2>;
214*4882a593Smuzhiyun			};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun			light-sensor@44 {
217*4882a593Smuzhiyun				compatible = "isil,isl29023";
218*4882a593Smuzhiyun				reg = <0x44>;
219*4882a593Smuzhiyun				interrupt-parent = <&gpio5>;
220*4882a593Smuzhiyun				interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
221*4882a593Smuzhiyun			};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun			magnetometer@e {
224*4882a593Smuzhiyun				compatible = "fsl,mag3110";
225*4882a593Smuzhiyun				reg = <0x0e>;
226*4882a593Smuzhiyun				interrupt-parent = <&gpio2>;
227*4882a593Smuzhiyun				interrupts = <29 IRQ_TYPE_EDGE_RISING>;
228*4882a593Smuzhiyun			};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun			accelerometer@1c {
231*4882a593Smuzhiyun				compatible = "fsl,mma8451";
232*4882a593Smuzhiyun				reg = <0x1c>;
233*4882a593Smuzhiyun				pinctrl-names = "default";
234*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_mma8451_int>;
235*4882a593Smuzhiyun				interrupt-parent = <&gpio6>;
236*4882a593Smuzhiyun				interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun		};
239*4882a593Smuzhiyun	};
240*4882a593Smuzhiyun};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun&ipu1_csi0_from_ipu1_csi0_mux {
243*4882a593Smuzhiyun	bus-width = <8>;
244*4882a593Smuzhiyun};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun&ipu1_csi0_mux_from_parallel_sensor {
247*4882a593Smuzhiyun	remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
248*4882a593Smuzhiyun	bus-width = <8>;
249*4882a593Smuzhiyun};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun&ipu1_csi0 {
252*4882a593Smuzhiyun	pinctrl-names = "default";
253*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ipu1_csi0>;
254*4882a593Smuzhiyun};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun&clks {
257*4882a593Smuzhiyun	assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
258*4882a593Smuzhiyun			  <&clks IMX6QDL_PLL4_BYPASS>,
259*4882a593Smuzhiyun			  <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
260*4882a593Smuzhiyun			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
261*4882a593Smuzhiyun			  <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
262*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
263*4882a593Smuzhiyun				 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
264*4882a593Smuzhiyun				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
265*4882a593Smuzhiyun				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
266*4882a593Smuzhiyun	assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
267*4882a593Smuzhiyun};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun&ecspi1 {
270*4882a593Smuzhiyun	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
271*4882a593Smuzhiyun	pinctrl-names = "default";
272*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
273*4882a593Smuzhiyun	status = "disabled"; /* pin conflict with WEIM NOR */
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun	flash: flash@0 {
276*4882a593Smuzhiyun		#address-cells = <1>;
277*4882a593Smuzhiyun		#size-cells = <1>;
278*4882a593Smuzhiyun		compatible = "st,m25p32", "jedec,spi-nor";
279*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
280*4882a593Smuzhiyun		reg = <0>;
281*4882a593Smuzhiyun	};
282*4882a593Smuzhiyun};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun&esai {
285*4882a593Smuzhiyun	pinctrl-names = "default";
286*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_esai>;
287*4882a593Smuzhiyun	assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
288*4882a593Smuzhiyun			  <&clks IMX6QDL_CLK_ESAI_EXTAL>;
289*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
290*4882a593Smuzhiyun	assigned-clock-rates = <0>, <24576000>;
291*4882a593Smuzhiyun	status = "okay";
292*4882a593Smuzhiyun};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun&fec {
295*4882a593Smuzhiyun	pinctrl-names = "default";
296*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
297*4882a593Smuzhiyun	phy-mode = "rgmii-id";
298*4882a593Smuzhiyun	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
299*4882a593Smuzhiyun			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
300*4882a593Smuzhiyun	fsl,err006687-workaround-present;
301*4882a593Smuzhiyun	status = "okay";
302*4882a593Smuzhiyun};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun&can1 {
305*4882a593Smuzhiyun	pinctrl-names = "default";
306*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
307*4882a593Smuzhiyun	xceiver-supply = <&reg_can_stby>;
308*4882a593Smuzhiyun	status = "disabled"; /* pin conflict with fec */
309*4882a593Smuzhiyun};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun&can2 {
312*4882a593Smuzhiyun	pinctrl-names = "default";
313*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan2>;
314*4882a593Smuzhiyun	xceiver-supply = <&reg_can_stby>;
315*4882a593Smuzhiyun	status = "okay";
316*4882a593Smuzhiyun};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun&gpmi {
319*4882a593Smuzhiyun	pinctrl-names = "default";
320*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_gpmi_nand>;
321*4882a593Smuzhiyun	status = "okay";
322*4882a593Smuzhiyun};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun&hdmi {
325*4882a593Smuzhiyun	pinctrl-names = "default";
326*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hdmi_cec>;
327*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c2>;
328*4882a593Smuzhiyun	status = "okay";
329*4882a593Smuzhiyun};
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun&i2c2 {
332*4882a593Smuzhiyun	clock-frequency = <100000>;
333*4882a593Smuzhiyun	pinctrl-names = "default";
334*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
335*4882a593Smuzhiyun	status = "okay";
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun	pmic: pfuze100@8 {
338*4882a593Smuzhiyun		compatible = "fsl,pfuze100";
339*4882a593Smuzhiyun		reg = <0x08>;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun		regulators {
342*4882a593Smuzhiyun			sw1a_reg: sw1ab {
343*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
344*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
345*4882a593Smuzhiyun				regulator-boot-on;
346*4882a593Smuzhiyun				regulator-always-on;
347*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
348*4882a593Smuzhiyun			};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun			sw1c_reg: sw1c {
351*4882a593Smuzhiyun				regulator-min-microvolt = <300000>;
352*4882a593Smuzhiyun				regulator-max-microvolt = <1875000>;
353*4882a593Smuzhiyun				regulator-boot-on;
354*4882a593Smuzhiyun				regulator-always-on;
355*4882a593Smuzhiyun				regulator-ramp-delay = <6250>;
356*4882a593Smuzhiyun			};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun			sw2_reg: sw2 {
359*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
360*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
361*4882a593Smuzhiyun				regulator-boot-on;
362*4882a593Smuzhiyun				regulator-always-on;
363*4882a593Smuzhiyun			};
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun			sw3a_reg: sw3a {
366*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
367*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
368*4882a593Smuzhiyun				regulator-boot-on;
369*4882a593Smuzhiyun				regulator-always-on;
370*4882a593Smuzhiyun			};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun			sw3b_reg: sw3b {
373*4882a593Smuzhiyun				regulator-min-microvolt = <400000>;
374*4882a593Smuzhiyun				regulator-max-microvolt = <1975000>;
375*4882a593Smuzhiyun				regulator-boot-on;
376*4882a593Smuzhiyun				regulator-always-on;
377*4882a593Smuzhiyun			};
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun			sw4_reg: sw4 {
380*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
381*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
382*4882a593Smuzhiyun			};
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun			swbst_reg: swbst {
385*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
386*4882a593Smuzhiyun				regulator-max-microvolt = <5150000>;
387*4882a593Smuzhiyun			};
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun			snvs_reg: vsnvs {
390*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
391*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
392*4882a593Smuzhiyun				regulator-boot-on;
393*4882a593Smuzhiyun				regulator-always-on;
394*4882a593Smuzhiyun			};
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun			vref_reg: vrefddr {
397*4882a593Smuzhiyun				regulator-boot-on;
398*4882a593Smuzhiyun				regulator-always-on;
399*4882a593Smuzhiyun			};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun			vgen1_reg: vgen1 {
402*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
403*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
404*4882a593Smuzhiyun			};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun			vgen2_reg: vgen2 {
407*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
408*4882a593Smuzhiyun				regulator-max-microvolt = <1550000>;
409*4882a593Smuzhiyun			};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun			vgen3_reg: vgen3 {
412*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
413*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
414*4882a593Smuzhiyun			};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun			vgen4_reg: vgen4 {
417*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
418*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
419*4882a593Smuzhiyun				regulator-always-on;
420*4882a593Smuzhiyun			};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun			vgen5_reg: vgen5 {
423*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
424*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
425*4882a593Smuzhiyun				regulator-always-on;
426*4882a593Smuzhiyun			};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun			vgen6_reg: vgen6 {
429*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
430*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
431*4882a593Smuzhiyun				regulator-always-on;
432*4882a593Smuzhiyun			};
433*4882a593Smuzhiyun		};
434*4882a593Smuzhiyun	};
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun	codec: cs42888@48 {
437*4882a593Smuzhiyun		compatible = "cirrus,cs42888";
438*4882a593Smuzhiyun		reg = <0x48>;
439*4882a593Smuzhiyun		clocks = <&codec_osc>;
440*4882a593Smuzhiyun		clock-names = "mclk";
441*4882a593Smuzhiyun		VA-supply = <&reg_audio>;
442*4882a593Smuzhiyun		VD-supply = <&reg_audio>;
443*4882a593Smuzhiyun		VLS-supply = <&reg_audio>;
444*4882a593Smuzhiyun		VLC-supply = <&reg_audio>;
445*4882a593Smuzhiyun	};
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun	touchscreen@4 {
448*4882a593Smuzhiyun		compatible = "eeti,egalax_ts";
449*4882a593Smuzhiyun		reg = <0x04>;
450*4882a593Smuzhiyun		pinctrl-names = "default";
451*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_egalax_int>;
452*4882a593Smuzhiyun		interrupt-parent = <&gpio2>;
453*4882a593Smuzhiyun		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
454*4882a593Smuzhiyun		wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
455*4882a593Smuzhiyun	};
456*4882a593Smuzhiyun};
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun&i2c3 {
459*4882a593Smuzhiyun	pinctrl-names = "default";
460*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
461*4882a593Smuzhiyun	status = "okay";
462*4882a593Smuzhiyun};
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun&iomuxc {
465*4882a593Smuzhiyun	pinctrl-names = "default";
466*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog>;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun	imx6qdl-sabreauto {
469*4882a593Smuzhiyun		pinctrl_hog: hoggrp {
470*4882a593Smuzhiyun			fsl,pins = <
471*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
472*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
473*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
474*4882a593Smuzhiyun			>;
475*4882a593Smuzhiyun		};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
478*4882a593Smuzhiyun			fsl,pins = <
479*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
480*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
481*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
482*4882a593Smuzhiyun			>;
483*4882a593Smuzhiyun		};
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun		pinctrl_ecspi1_cs: ecspi1cs {
486*4882a593Smuzhiyun			fsl,pins = <
487*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
488*4882a593Smuzhiyun			>;
489*4882a593Smuzhiyun		};
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun		pinctrl_egalax_int: egalax-intgrp {
492*4882a593Smuzhiyun			fsl,pins = <
493*4882a593Smuzhiyun				MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0xb0b1
494*4882a593Smuzhiyun			>;
495*4882a593Smuzhiyun		};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun		pinctrl_enet: enetgrp {
498*4882a593Smuzhiyun			fsl,pins = <
499*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0
500*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0
501*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
502*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
503*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
504*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
505*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
506*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
507*4882a593Smuzhiyun				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
508*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
509*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
510*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
511*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
512*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
513*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
514*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
515*4882a593Smuzhiyun			>;
516*4882a593Smuzhiyun		};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun		pinctrl_esai: esaigrp {
519*4882a593Smuzhiyun			fsl,pins = <
520*4882a593Smuzhiyun				MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
521*4882a593Smuzhiyun				MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
522*4882a593Smuzhiyun				MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
523*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
524*4882a593Smuzhiyun				MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
525*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
526*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
527*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
528*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
529*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
530*4882a593Smuzhiyun			>;
531*4882a593Smuzhiyun		};
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun		pinctrl_flexcan1: flexcan1grp {
534*4882a593Smuzhiyun			fsl,pins = <
535*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x17059
536*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x17059
537*4882a593Smuzhiyun			>;
538*4882a593Smuzhiyun		};
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun		pinctrl_flexcan2: flexcan2grp {
541*4882a593Smuzhiyun			fsl,pins = <
542*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x17059
543*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x17059
544*4882a593Smuzhiyun			>;
545*4882a593Smuzhiyun		};
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun		pinctrl_gpio_keys: gpiokeysgrp {
548*4882a593Smuzhiyun			fsl,pins = <
549*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CMD__GPIO1_IO11		0x1b0b0
550*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x1b0b0
551*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT4__GPIO2_IO12		0x1b0b0
552*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT7__GPIO2_IO15		0x1b0b0
553*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x1b0b0
554*4882a593Smuzhiyun			>;
555*4882a593Smuzhiyun		};
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun		pinctrl_gpio_leds: gpioledsgrp {
558*4882a593Smuzhiyun			fsl,pins = <
559*4882a593Smuzhiyun				MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15	0x80000000
560*4882a593Smuzhiyun			>;
561*4882a593Smuzhiyun		};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun		pinctrl_gpmi_nand: gpminandgrp {
564*4882a593Smuzhiyun			fsl,pins = <
565*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
566*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
567*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
568*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
569*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
570*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
571*4882a593Smuzhiyun				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
572*4882a593Smuzhiyun				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
573*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
574*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
575*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
576*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
577*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
578*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
579*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
580*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
581*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
582*4882a593Smuzhiyun			>;
583*4882a593Smuzhiyun		};
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun		pinctrl_hdmi_cec: hdmicecgrp {
586*4882a593Smuzhiyun			fsl,pins = <
587*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE	0x1f8b0
588*4882a593Smuzhiyun			>;
589*4882a593Smuzhiyun		};
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
592*4882a593Smuzhiyun			fsl,pins = <
593*4882a593Smuzhiyun				MX6QDL_PAD_EIM_EB2__I2C2_SCL	0x4001b8b1
594*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
595*4882a593Smuzhiyun			>;
596*4882a593Smuzhiyun		};
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun		pinctrl_i2c3: i2c3grp {
599*4882a593Smuzhiyun			fsl,pins = <
600*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
601*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
602*4882a593Smuzhiyun			>;
603*4882a593Smuzhiyun		};
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun		pinctrl_i2c3mux: i2c3muxgrp {
606*4882a593Smuzhiyun			fsl,pins = <
607*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
608*4882a593Smuzhiyun			>;
609*4882a593Smuzhiyun		};
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun		pinctrl_ipu1_csi0: ipu1csi0grp {
612*4882a593Smuzhiyun			fsl,pins = <
613*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x1b0b0
614*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x1b0b0
615*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x1b0b0
616*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x1b0b0
617*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x1b0b0
618*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x1b0b0
619*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x1b0b0
620*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x1b0b0
621*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
622*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x1b0b0
623*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x1b0b0
624*4882a593Smuzhiyun			>;
625*4882a593Smuzhiyun		};
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun		pinctrl_max7310: max7310grp {
628*4882a593Smuzhiyun			fsl,pins = <
629*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
630*4882a593Smuzhiyun			>;
631*4882a593Smuzhiyun		};
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun		pinctrl_mma8451_int: mma8451intgrp {
634*4882a593Smuzhiyun			fsl,pins = <
635*4882a593Smuzhiyun				MX6QDL_PAD_EIM_BCLK__GPIO6_IO31		0xb0b1
636*4882a593Smuzhiyun			>;
637*4882a593Smuzhiyun		};
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun		pinctrl_pwm3: pwm1grp {
640*4882a593Smuzhiyun			fsl,pins = <
641*4882a593Smuzhiyun				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
642*4882a593Smuzhiyun			>;
643*4882a593Smuzhiyun		};
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun		pinctrl_gpt_input_capture0: gptinputcapture0grp {
646*4882a593Smuzhiyun			fsl,pins = <
647*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1	0x1b0b0
648*4882a593Smuzhiyun			>;
649*4882a593Smuzhiyun		};
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun		pinctrl_gpt_input_capture1: gptinputcapture1grp {
652*4882a593Smuzhiyun			fsl,pins = <
653*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2	0x1b0b0
654*4882a593Smuzhiyun			>;
655*4882a593Smuzhiyun		};
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun		pinctrl_spdif: spdifgrp {
658*4882a593Smuzhiyun			fsl,pins = <
659*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
660*4882a593Smuzhiyun			>;
661*4882a593Smuzhiyun		};
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun		pinctrl_uart4: uart4grp {
664*4882a593Smuzhiyun			fsl,pins = <
665*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
666*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
667*4882a593Smuzhiyun			>;
668*4882a593Smuzhiyun		};
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun		pinctrl_usbotg: usbotggrp {
671*4882a593Smuzhiyun			fsl,pins = <
672*4882a593Smuzhiyun				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
673*4882a593Smuzhiyun			>;
674*4882a593Smuzhiyun		};
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun		pinctrl_usdhc3: usdhc3grp {
677*4882a593Smuzhiyun			fsl,pins = <
678*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
679*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
680*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
681*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
682*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
683*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
684*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
685*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
686*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
687*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
688*4882a593Smuzhiyun			>;
689*4882a593Smuzhiyun		};
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
692*4882a593Smuzhiyun			fsl,pins = <
693*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170b9
694*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100b9
695*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170b9
696*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170b9
697*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170b9
698*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170b9
699*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170b9
700*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170b9
701*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170b9
702*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170b9
703*4882a593Smuzhiyun			>;
704*4882a593Smuzhiyun		};
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
707*4882a593Smuzhiyun			fsl,pins = <
708*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x170f9
709*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x100f9
710*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x170f9
711*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x170f9
712*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x170f9
713*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
714*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x170f9
715*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x170f9
716*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x170f9
717*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x170f9
718*4882a593Smuzhiyun			>;
719*4882a593Smuzhiyun		};
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun		pinctrl_weim_cs0: weimcs0grp {
722*4882a593Smuzhiyun			fsl,pins = <
723*4882a593Smuzhiyun				MX6QDL_PAD_EIM_CS0__EIM_CS0_B		0xb0b1
724*4882a593Smuzhiyun			>;
725*4882a593Smuzhiyun		};
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun		pinctrl_weim_nor: weimnorgrp {
728*4882a593Smuzhiyun			fsl,pins = <
729*4882a593Smuzhiyun				MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0b1
730*4882a593Smuzhiyun				MX6QDL_PAD_EIM_RW__EIM_RW		0xb0b1
731*4882a593Smuzhiyun				MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B		0xb060
732*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D16__EIM_DATA16		0x1b0b0
733*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D17__EIM_DATA17		0x1b0b0
734*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D18__EIM_DATA18		0x1b0b0
735*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D19__EIM_DATA19		0x1b0b0
736*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D20__EIM_DATA20		0x1b0b0
737*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D21__EIM_DATA21		0x1b0b0
738*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D22__EIM_DATA22		0x1b0b0
739*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D23__EIM_DATA23		0x1b0b0
740*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D24__EIM_DATA24		0x1b0b0
741*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D25__EIM_DATA25		0x1b0b0
742*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D26__EIM_DATA26		0x1b0b0
743*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D27__EIM_DATA27		0x1b0b0
744*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D28__EIM_DATA28		0x1b0b0
745*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D29__EIM_DATA29		0x1b0b0
746*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D30__EIM_DATA30		0x1b0b0
747*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D31__EIM_DATA31		0x1b0b0
748*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A23__EIM_ADDR23		0xb0b1
749*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A22__EIM_ADDR22		0xb0b1
750*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A21__EIM_ADDR21		0xb0b1
751*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A20__EIM_ADDR20		0xb0b1
752*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A19__EIM_ADDR19		0xb0b1
753*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A18__EIM_ADDR18		0xb0b1
754*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A17__EIM_ADDR17		0xb0b1
755*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A16__EIM_ADDR16		0xb0b1
756*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0b1
757*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0b1
758*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0b1
759*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0b1
760*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0b1
761*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0b1
762*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0b1
763*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0b1
764*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0b1
765*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0b1
766*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0b1
767*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0b1
768*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0b1
769*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0b1
770*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0b1
771*4882a593Smuzhiyun				MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
772*4882a593Smuzhiyun			>;
773*4882a593Smuzhiyun		};
774*4882a593Smuzhiyun	};
775*4882a593Smuzhiyun};
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun&ldb {
778*4882a593Smuzhiyun	status = "okay";
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun	lvds-channel@0 {
781*4882a593Smuzhiyun		fsl,data-mapping = "spwg";
782*4882a593Smuzhiyun		fsl,data-width = <18>;
783*4882a593Smuzhiyun		status = "okay";
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun		display-timings {
786*4882a593Smuzhiyun			native-mode = <&timing0>;
787*4882a593Smuzhiyun			timing0: hsd100pxn1 {
788*4882a593Smuzhiyun				clock-frequency = <65000000>;
789*4882a593Smuzhiyun				hactive = <1024>;
790*4882a593Smuzhiyun				vactive = <768>;
791*4882a593Smuzhiyun				hback-porch = <220>;
792*4882a593Smuzhiyun				hfront-porch = <40>;
793*4882a593Smuzhiyun				vback-porch = <21>;
794*4882a593Smuzhiyun				vfront-porch = <7>;
795*4882a593Smuzhiyun				hsync-len = <60>;
796*4882a593Smuzhiyun				vsync-len = <10>;
797*4882a593Smuzhiyun			};
798*4882a593Smuzhiyun		};
799*4882a593Smuzhiyun	};
800*4882a593Smuzhiyun};
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun&pwm3 {
803*4882a593Smuzhiyun	#pwm-cells = <2>;
804*4882a593Smuzhiyun	pinctrl-names = "default";
805*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
806*4882a593Smuzhiyun	status = "okay";
807*4882a593Smuzhiyun};
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun&pcie {
810*4882a593Smuzhiyun	status = "okay";
811*4882a593Smuzhiyun};
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun&spdif {
814*4882a593Smuzhiyun	pinctrl-names = "default";
815*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_spdif>;
816*4882a593Smuzhiyun	status = "okay";
817*4882a593Smuzhiyun};
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun&uart4 {
820*4882a593Smuzhiyun	pinctrl-names = "default";
821*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart4>;
822*4882a593Smuzhiyun	status = "okay";
823*4882a593Smuzhiyun};
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun&usbh1 {
826*4882a593Smuzhiyun	vbus-supply = <&reg_usb_h1_vbus>;
827*4882a593Smuzhiyun	status = "okay";
828*4882a593Smuzhiyun};
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun&usbotg {
831*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
832*4882a593Smuzhiyun	pinctrl-names = "default";
833*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
834*4882a593Smuzhiyun	status = "okay";
835*4882a593Smuzhiyun};
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun&usdhc3 {
838*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
839*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
840*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
841*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
842*4882a593Smuzhiyun	cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
843*4882a593Smuzhiyun	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
844*4882a593Smuzhiyun	status = "okay";
845*4882a593Smuzhiyun};
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun&weim {
848*4882a593Smuzhiyun	pinctrl-names = "default";
849*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
850*4882a593Smuzhiyun	ranges = <0 0 0x08000000 0x08000000>;
851*4882a593Smuzhiyun	status = "disabled"; /* pin conflict with SPI NOR */
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun	nor@0,0 {
854*4882a593Smuzhiyun		compatible = "cfi-flash";
855*4882a593Smuzhiyun		reg = <0 0 0x02000000>;
856*4882a593Smuzhiyun		#address-cells = <1>;
857*4882a593Smuzhiyun		#size-cells = <1>;
858*4882a593Smuzhiyun		bank-width = <2>;
859*4882a593Smuzhiyun		fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
860*4882a593Smuzhiyun				0x0000c000 0x1404a38e 0x00000000>;
861*4882a593Smuzhiyun	};
862*4882a593Smuzhiyun};
863