1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ OR MIT 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Copyright 2017 NXP 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun#include "imx6qdl-pico.dtsi" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun leds { 9*4882a593Smuzhiyun compatible = "gpio-leds"; 10*4882a593Smuzhiyun pinctrl-names = "default"; 11*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun led { 14*4882a593Smuzhiyun label = "gpio-led"; 15*4882a593Smuzhiyun gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun}; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun&i2c1 { 22*4882a593Smuzhiyun mpl3115@60 { 23*4882a593Smuzhiyun compatible = "fsl,mpl3115"; 24*4882a593Smuzhiyun reg = <0x60>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun&i2c2 { 29*4882a593Smuzhiyun io-expander@25 { 30*4882a593Smuzhiyun compatible = "nxp,pca9554"; 31*4882a593Smuzhiyun reg = <0x25>; 32*4882a593Smuzhiyun gpio-controller; 33*4882a593Smuzhiyun #gpio-cells = <2>; 34*4882a593Smuzhiyun #interrupt-cells = <2>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&iomuxc { 40*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 41*4882a593Smuzhiyun fsl,pins = < 42*4882a593Smuzhiyun MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 43*4882a593Smuzhiyun >; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun}; 46