xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/imx6qdl-phytec-mira.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2018 PHYTEC Messtechnik GmbH
4*4882a593Smuzhiyun * Author: Christian Hemp <c.hemp@phytec.de>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	aliases {
10*4882a593Smuzhiyun		rtc0 = &i2c_rtc;
11*4882a593Smuzhiyun	};
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	backlight: backlight {
14*4882a593Smuzhiyun		compatible = "pwm-backlight";
15*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
16*4882a593Smuzhiyun		default-brightness-level = <7>;
17*4882a593Smuzhiyun		power-supply = <&reg_backlight>;
18*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
19*4882a593Smuzhiyun		status = "okay";
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	gpio_leds: leds {
23*4882a593Smuzhiyun		compatible = "gpio-leds";
24*4882a593Smuzhiyun		pinctrl-names = "default";
25*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpioleds>;
26*4882a593Smuzhiyun		status = "disabled";
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		red {
29*4882a593Smuzhiyun			label = "phyboard-mira:red";
30*4882a593Smuzhiyun			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		green {
34*4882a593Smuzhiyun			label = "phyboard-mira:green";
35*4882a593Smuzhiyun			gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
36*4882a593Smuzhiyun		};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		blue {
39*4882a593Smuzhiyun			label = "phyboard-mira:blue";
40*4882a593Smuzhiyun			gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
41*4882a593Smuzhiyun			linux,default-trigger = "mmc0";
42*4882a593Smuzhiyun		};
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	reg_backlight: regulator-backlight {
46*4882a593Smuzhiyun		compatible = "regulator-fixed";
47*4882a593Smuzhiyun		regulator-name = "backlight_3v3";
48*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
49*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
50*4882a593Smuzhiyun		regulator-always-on;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	reg_en_switch: regulator-en-switch {
54*4882a593Smuzhiyun		compatible = "regulator-fixed";
55*4882a593Smuzhiyun		pinctrl-names = "default";
56*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_en_switch>;
57*4882a593Smuzhiyun		regulator-name = "Enable Switch";
58*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
59*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
60*4882a593Smuzhiyun		enable-active-high;
61*4882a593Smuzhiyun		gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
62*4882a593Smuzhiyun		regulator-always-on;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	reg_flexcan1: regulator-flexcan1 {
66*4882a593Smuzhiyun		compatible = "regulator-fixed";
67*4882a593Smuzhiyun		pinctrl-names = "default";
68*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_flexcan1_en>;
69*4882a593Smuzhiyun		regulator-name = "flexcan1-reg";
70*4882a593Smuzhiyun		regulator-min-microvolt = <1500000>;
71*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
72*4882a593Smuzhiyun		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
73*4882a593Smuzhiyun		enable-active-high;
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	reg_panel: regulator-panel {
77*4882a593Smuzhiyun		compatible = "regulator-fixed";
78*4882a593Smuzhiyun		regulator-name = "panel-power-supply";
79*4882a593Smuzhiyun		regulator-min-microvolt = <12000000>;
80*4882a593Smuzhiyun		regulator-max-microvolt = <12000000>;
81*4882a593Smuzhiyun		regulator-always-on;
82*4882a593Smuzhiyun	};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun	reg_pcie: regulator-pcie {
85*4882a593Smuzhiyun		compatible = "regulator-fixed";
86*4882a593Smuzhiyun		pinctrl-names = "default";
87*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_pcie_reg>;
88*4882a593Smuzhiyun		regulator-name = "mPCIe_1V5";
89*4882a593Smuzhiyun		regulator-min-microvolt = <1500000>;
90*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
91*4882a593Smuzhiyun		gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>;
92*4882a593Smuzhiyun		enable-active-high;
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun	reg_usb_h1_vbus: usb-h1-vbus {
96*4882a593Smuzhiyun		compatible = "regulator-fixed";
97*4882a593Smuzhiyun		pinctrl-names = "default";
98*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbh1_vbus>;
99*4882a593Smuzhiyun		regulator-name = "usb_h1_vbus";
100*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
101*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
102*4882a593Smuzhiyun		gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
103*4882a593Smuzhiyun		enable-active-high;
104*4882a593Smuzhiyun	};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun	reg_usbotg_vbus: usbotg-vbus {
107*4882a593Smuzhiyun		compatible = "regulator-fixed";
108*4882a593Smuzhiyun		pinctrl-names = "default";
109*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usbotg_vbus>;
110*4882a593Smuzhiyun		regulator-name = "usb_otg_vbus";
111*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
112*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
113*4882a593Smuzhiyun		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
114*4882a593Smuzhiyun		enable-active-high;
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	panel {
118*4882a593Smuzhiyun		compatible = "auo,g104sn02";
119*4882a593Smuzhiyun		pinctrl-names = "default";
120*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_panel_en>;
121*4882a593Smuzhiyun		power-supply = <&reg_panel>;
122*4882a593Smuzhiyun		enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
123*4882a593Smuzhiyun		backlight = <&backlight>;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun		port {
126*4882a593Smuzhiyun			panel_in: endpoint {
127*4882a593Smuzhiyun				remote-endpoint = <&lvds0_out>;
128*4882a593Smuzhiyun			};
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun	};
131*4882a593Smuzhiyun};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun&can1 {
134*4882a593Smuzhiyun	pinctrl-names = "default";
135*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_flexcan1>;
136*4882a593Smuzhiyun	xceiver-supply = <&reg_flexcan1>;
137*4882a593Smuzhiyun	status = "disabled";
138*4882a593Smuzhiyun};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun&hdmi {
141*4882a593Smuzhiyun	pinctrl-names = "default";
142*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hdmicec>;
143*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c2>;
144*4882a593Smuzhiyun	status = "disabled";
145*4882a593Smuzhiyun};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun&i2c1 {
148*4882a593Smuzhiyun	pinctrl-names = "default";
149*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
150*4882a593Smuzhiyun	clock-frequency = <400000>;
151*4882a593Smuzhiyun	status = "disabled";
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun	stmpe: touchctrl@44 {
154*4882a593Smuzhiyun		compatible = "st,stmpe811";
155*4882a593Smuzhiyun		pinctrl-names = "default";
156*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_stmpe>;
157*4882a593Smuzhiyun		reg = <0x44>;
158*4882a593Smuzhiyun		interrupt-parent = <&gpio7>;
159*4882a593Smuzhiyun		interrupts = <12 IRQ_TYPE_NONE>;
160*4882a593Smuzhiyun		status = "disabled";
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun		stmpe_touchscreen {
163*4882a593Smuzhiyun			compatible = "st,stmpe-ts";
164*4882a593Smuzhiyun			st,sample-time = <4>;
165*4882a593Smuzhiyun			st,mod-12b = <1>;
166*4882a593Smuzhiyun			st,ref-sel = <0>;
167*4882a593Smuzhiyun			st,adc-freq = <1>;
168*4882a593Smuzhiyun			st,ave-ctrl = <1>;
169*4882a593Smuzhiyun			st,touch-det-delay = <2>;
170*4882a593Smuzhiyun			st,settling = <2>;
171*4882a593Smuzhiyun			st,fraction-z = <7>;
172*4882a593Smuzhiyun			st,i-drive = <1>;
173*4882a593Smuzhiyun		};
174*4882a593Smuzhiyun	};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun	i2c_rtc: rtc@68 {
177*4882a593Smuzhiyun		compatible = "microcrystal,rv4162";
178*4882a593Smuzhiyun		pinctrl-names = "default";
179*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_rtc_int>;
180*4882a593Smuzhiyun		reg = <0x68>;
181*4882a593Smuzhiyun		interrupt-parent = <&gpio7>;
182*4882a593Smuzhiyun		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
183*4882a593Smuzhiyun		status = "disabled";
184*4882a593Smuzhiyun	};
185*4882a593Smuzhiyun};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun&i2c2 {
188*4882a593Smuzhiyun	pinctrl-names = "default";
189*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
190*4882a593Smuzhiyun	clock-frequency = <100000>;
191*4882a593Smuzhiyun	status = "disabled";
192*4882a593Smuzhiyun};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun&ldb {
195*4882a593Smuzhiyun	status = "okay";
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun	lvds-channel@0 {
198*4882a593Smuzhiyun		fsl,data-mapping = "spwg";
199*4882a593Smuzhiyun		fsl,data-width = <24>;
200*4882a593Smuzhiyun		status = "disabled";
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun		port@4 {
203*4882a593Smuzhiyun			reg = <4>;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun			lvds0_out: endpoint {
206*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
207*4882a593Smuzhiyun			};
208*4882a593Smuzhiyun		};
209*4882a593Smuzhiyun	};
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&pcie {
213*4882a593Smuzhiyun	pinctrl-names = "default";
214*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pcie>;
215*4882a593Smuzhiyun	reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
216*4882a593Smuzhiyun	vpcie-supply = <&reg_pcie>;
217*4882a593Smuzhiyun	status = "disabled";
218*4882a593Smuzhiyun};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun&pwm1 {
221*4882a593Smuzhiyun	#pwm-cells = <2>;
222*4882a593Smuzhiyun	pinctrl-names = "default";
223*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
224*4882a593Smuzhiyun	status = "okay";
225*4882a593Smuzhiyun};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun&uart2 {
228*4882a593Smuzhiyun	pinctrl-names = "default";
229*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
230*4882a593Smuzhiyun	status = "okay";
231*4882a593Smuzhiyun};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun&uart3 {
234*4882a593Smuzhiyun	pinctrl-names = "default";
235*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
236*4882a593Smuzhiyun	uart-has-rtscts;
237*4882a593Smuzhiyun	status = "disabled";
238*4882a593Smuzhiyun};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun&usbh1 {
241*4882a593Smuzhiyun	vbus-supply = <&reg_usb_h1_vbus>;
242*4882a593Smuzhiyun	disable-over-current;
243*4882a593Smuzhiyun	status = "disabled";
244*4882a593Smuzhiyun};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun&usbotg {
247*4882a593Smuzhiyun	pinctrl-names = "default";
248*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
249*4882a593Smuzhiyun	vbus-supply = <&reg_usbotg_vbus>;
250*4882a593Smuzhiyun	disable-over-current;
251*4882a593Smuzhiyun	status = "disabled";
252*4882a593Smuzhiyun};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun&usdhc1 {
255*4882a593Smuzhiyun	pinctrl-names = "default";
256*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
257*4882a593Smuzhiyun	cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>;
258*4882a593Smuzhiyun	no-1-8-v;
259*4882a593Smuzhiyun	status = "disabled";
260*4882a593Smuzhiyun};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun&iomuxc {
263*4882a593Smuzhiyun	pinctrl_panel_en: panelen1grp {
264*4882a593Smuzhiyun		fsl,pins = <
265*4882a593Smuzhiyun			MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0xb0b1
266*4882a593Smuzhiyun		>;
267*4882a593Smuzhiyun	};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun	pinctrl_en_switch: enswitchgrp {
270*4882a593Smuzhiyun		fsl,pins = <
271*4882a593Smuzhiyun			MX6QDL_PAD_EIM_DA4__GPIO3_IO04		0xb0b1
272*4882a593Smuzhiyun		>;
273*4882a593Smuzhiyun	};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun	pinctrl_flexcan1: flexcan1grp {
276*4882a593Smuzhiyun		fsl,pins = <
277*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX		0x1b0b0
278*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x1b0b0
279*4882a593Smuzhiyun		>;
280*4882a593Smuzhiyun	};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun	pinctrl_flexcan1_en: flexcan1engrp {
283*4882a593Smuzhiyun		fsl,pins = <
284*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A18__GPIO2_IO20		0xb0b1
285*4882a593Smuzhiyun		>;
286*4882a593Smuzhiyun	};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun	pinctrl_gpioleds: gpioledsgrp {
289*4882a593Smuzhiyun		fsl,pins = <
290*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22	0x1b0b0
291*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23	0x1b0b0
292*4882a593Smuzhiyun			MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24	0x1b0b0
293*4882a593Smuzhiyun		>;
294*4882a593Smuzhiyun	};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	pinctrl_hdmicec: hdmicecgrp {
297*4882a593Smuzhiyun		fsl,pins = <
298*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
299*4882a593Smuzhiyun		>;
300*4882a593Smuzhiyun	};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
303*4882a593Smuzhiyun		fsl,pins = <
304*4882a593Smuzhiyun			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
305*4882a593Smuzhiyun			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
306*4882a593Smuzhiyun		>;
307*4882a593Smuzhiyun	};
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
310*4882a593Smuzhiyun		fsl,pins = <
311*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
312*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
313*4882a593Smuzhiyun		>;
314*4882a593Smuzhiyun	};
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun	pinctrl_pcie: pciegrp {
317*4882a593Smuzhiyun		fsl,pins = <
318*4882a593Smuzhiyun			MX6QDL_PAD_EIM_OE__GPIO2_IO25		0xb0b1
319*4882a593Smuzhiyun		>;
320*4882a593Smuzhiyun	};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun	pinctrl_pcie_reg: pciereggrp {
323*4882a593Smuzhiyun		fsl,pins = <
324*4882a593Smuzhiyun			MX6QDL_PAD_EIM_DA0__GPIO3_IO00		0xb0b1
325*4882a593Smuzhiyun		>;
326*4882a593Smuzhiyun	};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun	pinctrl_pwm1: pwm1grp {
329*4882a593Smuzhiyun		fsl,pins = <
330*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_9__PWM1_OUT		0x1b0b1
331*4882a593Smuzhiyun		>;
332*4882a593Smuzhiyun	};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun	pinctrl_rtc_int: rtcintgrp {
335*4882a593Smuzhiyun		fsl,pins = <
336*4882a593Smuzhiyun			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x1b0b0
337*4882a593Smuzhiyun		>;
338*4882a593Smuzhiyun	};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun	pinctrl_stmpe: stmpegrp {
341*4882a593Smuzhiyun		fsl,pins = <
342*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0
343*4882a593Smuzhiyun		>;
344*4882a593Smuzhiyun	};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
347*4882a593Smuzhiyun		fsl,pins = <
348*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
349*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
350*4882a593Smuzhiyun		>;
351*4882a593Smuzhiyun	};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
354*4882a593Smuzhiyun		fsl,pins = <
355*4882a593Smuzhiyun			MX6QDL_PAD_EIM_EB3__UART3_CTS_B		0x1b0b1
356*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D23__UART3_RTS_B		0x1b0b1
357*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
358*4882a593Smuzhiyun			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
359*4882a593Smuzhiyun		>;
360*4882a593Smuzhiyun	};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun	pinctrl_usbh1_vbus: usbh1vbusgrp {
363*4882a593Smuzhiyun		fsl,pins = <
364*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A20__GPIO2_IO18		0xb0b1
365*4882a593Smuzhiyun		>;
366*4882a593Smuzhiyun	};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun	pinctrl_usbotg: usbotggrp {
369*4882a593Smuzhiyun		fsl,pins = <
370*4882a593Smuzhiyun			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
371*4882a593Smuzhiyun		>;
372*4882a593Smuzhiyun	};
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun	pinctrl_usbotg_vbus: usbotgvbusgrp {
375*4882a593Smuzhiyun		fsl,pins = <
376*4882a593Smuzhiyun			MX6QDL_PAD_EIM_A19__GPIO2_IO19		0xb0b1
377*4882a593Smuzhiyun		>;
378*4882a593Smuzhiyun	};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
381*4882a593Smuzhiyun		fsl,pins = <
382*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CMD__SD1_CMD		0x170f9
383*4882a593Smuzhiyun			MX6QDL_PAD_SD1_CLK__SD1_CLK		0x100f9
384*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x170f9
385*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x170f9
386*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x170f9
387*4882a593Smuzhiyun			MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x170f9
388*4882a593Smuzhiyun			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31		0xb0b1  /* CD */
389*4882a593Smuzhiyun		>;
390*4882a593Smuzhiyun	};
391*4882a593Smuzhiyun};
392