xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm/imx6qdl-nit6xlite.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 OR X11
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2015 Boundary Devices, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
6*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	chosen {
10*4882a593Smuzhiyun		stdout-path = &uart2;
11*4882a593Smuzhiyun	};
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	memory@10000000 {
14*4882a593Smuzhiyun		device_type = "memory";
15*4882a593Smuzhiyun		reg = <0x10000000 0x20000000>;
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	regulators {
19*4882a593Smuzhiyun		compatible = "simple-bus";
20*4882a593Smuzhiyun		#address-cells = <1>;
21*4882a593Smuzhiyun		#size-cells = <0>;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun		reg_2p5v: regulator@0 {
24*4882a593Smuzhiyun			compatible = "regulator-fixed";
25*4882a593Smuzhiyun			reg = <0>;
26*4882a593Smuzhiyun			regulator-name = "2P5V";
27*4882a593Smuzhiyun			regulator-min-microvolt = <2500000>;
28*4882a593Smuzhiyun			regulator-max-microvolt = <2500000>;
29*4882a593Smuzhiyun			regulator-always-on;
30*4882a593Smuzhiyun		};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		reg_3p3v: regulator@1 {
33*4882a593Smuzhiyun			compatible = "regulator-fixed";
34*4882a593Smuzhiyun			reg = <1>;
35*4882a593Smuzhiyun			regulator-name = "3P3V";
36*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
37*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
38*4882a593Smuzhiyun			regulator-always-on;
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun		reg_usb_otg_vbus: regulator@2 {
42*4882a593Smuzhiyun			compatible = "regulator-fixed";
43*4882a593Smuzhiyun			reg = <2>;
44*4882a593Smuzhiyun			regulator-name = "usb_otg_vbus";
45*4882a593Smuzhiyun			regulator-min-microvolt = <5000000>;
46*4882a593Smuzhiyun			regulator-max-microvolt = <5000000>;
47*4882a593Smuzhiyun			gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
48*4882a593Smuzhiyun			enable-active-high;
49*4882a593Smuzhiyun		};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun		reg_wlan_vmmc: regulator@3 {
52*4882a593Smuzhiyun			compatible = "regulator-fixed";
53*4882a593Smuzhiyun			reg = <3>;
54*4882a593Smuzhiyun			pinctrl-names = "default";
55*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_wlan_vmmc>;
56*4882a593Smuzhiyun			regulator-name = "reg_wlan_vmmc";
57*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
58*4882a593Smuzhiyun			regulator-max-microvolt = <1800000>;
59*4882a593Smuzhiyun			gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>;
60*4882a593Smuzhiyun			startup-delay-us = <70000>;
61*4882a593Smuzhiyun			enable-active-high;
62*4882a593Smuzhiyun		};
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	gpio-keys {
66*4882a593Smuzhiyun		compatible = "gpio-keys";
67*4882a593Smuzhiyun		pinctrl-names = "default";
68*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_keys>;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		home {
71*4882a593Smuzhiyun			label = "Home";
72*4882a593Smuzhiyun			gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>;
73*4882a593Smuzhiyun			linux,code = <102>;
74*4882a593Smuzhiyun		};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun		back {
77*4882a593Smuzhiyun			label = "Back";
78*4882a593Smuzhiyun			gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>;
79*4882a593Smuzhiyun			linux,code = <158>;
80*4882a593Smuzhiyun		};
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	leds {
84*4882a593Smuzhiyun		compatible = "gpio-leds";
85*4882a593Smuzhiyun		pinctrl-names = "default";
86*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_leds>;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun		j14-pin1 {
89*4882a593Smuzhiyun			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
90*4882a593Smuzhiyun			retain-state-suspended;
91*4882a593Smuzhiyun			default-state = "off";
92*4882a593Smuzhiyun		};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun		j14-pin3 {
95*4882a593Smuzhiyun			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
96*4882a593Smuzhiyun			retain-state-suspended;
97*4882a593Smuzhiyun			default-state = "off";
98*4882a593Smuzhiyun		};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun		j14-pins8-9 {
101*4882a593Smuzhiyun			gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
102*4882a593Smuzhiyun			retain-state-suspended;
103*4882a593Smuzhiyun			default-state = "off";
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun		j46-pin2 {
107*4882a593Smuzhiyun			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
108*4882a593Smuzhiyun			retain-state-suspended;
109*4882a593Smuzhiyun			default-state = "off";
110*4882a593Smuzhiyun		};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun		j46-pin3 {
113*4882a593Smuzhiyun			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
114*4882a593Smuzhiyun			retain-state-suspended;
115*4882a593Smuzhiyun			default-state = "off";
116*4882a593Smuzhiyun		};
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun	backlight-lcd {
120*4882a593Smuzhiyun		compatible = "pwm-backlight";
121*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
122*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
123*4882a593Smuzhiyun		default-brightness-level = <7>;
124*4882a593Smuzhiyun		power-supply = <&reg_3p3v>;
125*4882a593Smuzhiyun		status = "okay";
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	backlight_lvds0: backlight-lvds0 {
129*4882a593Smuzhiyun		compatible = "pwm-backlight";
130*4882a593Smuzhiyun		pwms = <&pwm4 0 5000000>;
131*4882a593Smuzhiyun		brightness-levels = <0 4 8 16 32 64 128 255>;
132*4882a593Smuzhiyun		default-brightness-level = <7>;
133*4882a593Smuzhiyun		power-supply = <&reg_3p3v>;
134*4882a593Smuzhiyun		status = "okay";
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	panel-lvds0 {
138*4882a593Smuzhiyun		compatible = "hannstar,hsd100pxn1";
139*4882a593Smuzhiyun		backlight = <&backlight_lvds0>;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		port {
142*4882a593Smuzhiyun			panel_in_lvds0: endpoint {
143*4882a593Smuzhiyun				remote-endpoint = <&lvds0_out>;
144*4882a593Smuzhiyun			};
145*4882a593Smuzhiyun		};
146*4882a593Smuzhiyun	};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun	sound {
149*4882a593Smuzhiyun		compatible = "fsl,imx6dl-nit6xlite-sgtl5000",
150*4882a593Smuzhiyun			     "fsl,imx-audio-sgtl5000";
151*4882a593Smuzhiyun		model = "imx6dl-nit6xlite-sgtl5000";
152*4882a593Smuzhiyun		ssi-controller = <&ssi1>;
153*4882a593Smuzhiyun		audio-codec = <&codec>;
154*4882a593Smuzhiyun		audio-routing =
155*4882a593Smuzhiyun			"MIC_IN", "Mic Jack",
156*4882a593Smuzhiyun			"Mic Jack", "Mic Bias",
157*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT";
158*4882a593Smuzhiyun		mux-int-port = <1>;
159*4882a593Smuzhiyun		mux-ext-port = <3>;
160*4882a593Smuzhiyun	};
161*4882a593Smuzhiyun};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun&audmux {
164*4882a593Smuzhiyun	pinctrl-names = "default";
165*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_audmux>;
166*4882a593Smuzhiyun	status = "okay";
167*4882a593Smuzhiyun};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun&clks {
170*4882a593Smuzhiyun	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
171*4882a593Smuzhiyun			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
172*4882a593Smuzhiyun	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
173*4882a593Smuzhiyun				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
174*4882a593Smuzhiyun};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun&ecspi1 {
177*4882a593Smuzhiyun	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
178*4882a593Smuzhiyun	pinctrl-names = "default";
179*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_ecspi1>;
180*4882a593Smuzhiyun	status = "okay";
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	flash: flash@0 {
183*4882a593Smuzhiyun		compatible = "microchip,sst25vf016b";
184*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
185*4882a593Smuzhiyun		reg = <0>;
186*4882a593Smuzhiyun	};
187*4882a593Smuzhiyun};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun&fec {
190*4882a593Smuzhiyun	pinctrl-names = "default";
191*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_enet>;
192*4882a593Smuzhiyun	phy-mode = "rgmii";
193*4882a593Smuzhiyun	phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
194*4882a593Smuzhiyun	txen-skew-ps = <0>;
195*4882a593Smuzhiyun	txc-skew-ps = <3000>;
196*4882a593Smuzhiyun	rxdv-skew-ps = <0>;
197*4882a593Smuzhiyun	rxc-skew-ps = <3000>;
198*4882a593Smuzhiyun	rxd0-skew-ps = <0>;
199*4882a593Smuzhiyun	rxd1-skew-ps = <0>;
200*4882a593Smuzhiyun	rxd2-skew-ps = <0>;
201*4882a593Smuzhiyun	rxd3-skew-ps = <0>;
202*4882a593Smuzhiyun	txd0-skew-ps = <0>;
203*4882a593Smuzhiyun	txd1-skew-ps = <0>;
204*4882a593Smuzhiyun	txd2-skew-ps = <0>;
205*4882a593Smuzhiyun	txd3-skew-ps = <0>;
206*4882a593Smuzhiyun	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
207*4882a593Smuzhiyun			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
208*4882a593Smuzhiyun	fsl,err006687-workaround-present;
209*4882a593Smuzhiyun	status = "okay";
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&hdmi {
213*4882a593Smuzhiyun	ddc-i2c-bus = <&i2c2>;
214*4882a593Smuzhiyun	status = "okay";
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&i2c1 {
218*4882a593Smuzhiyun	clock-frequency = <100000>;
219*4882a593Smuzhiyun	pinctrl-names = "default";
220*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
221*4882a593Smuzhiyun	status = "okay";
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	codec: sgtl5000@a {
224*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
225*4882a593Smuzhiyun		pinctrl-names = "default";
226*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_sgtl5000>;
227*4882a593Smuzhiyun		reg = <0x0a>;
228*4882a593Smuzhiyun		clocks = <&clks IMX6QDL_CLK_CKO>;
229*4882a593Smuzhiyun		VDDA-supply = <&reg_2p5v>;
230*4882a593Smuzhiyun		VDDIO-supply = <&reg_3p3v>;
231*4882a593Smuzhiyun	};
232*4882a593Smuzhiyun};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun&i2c2 {
235*4882a593Smuzhiyun	clock-frequency = <100000>;
236*4882a593Smuzhiyun	pinctrl-names = "default";
237*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
238*4882a593Smuzhiyun	status = "okay";
239*4882a593Smuzhiyun};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun&i2c3 {
242*4882a593Smuzhiyun	clock-frequency = <100000>;
243*4882a593Smuzhiyun	pinctrl-names = "default";
244*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
245*4882a593Smuzhiyun	status = "okay";
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun	touchscreen@4 {
248*4882a593Smuzhiyun		compatible = "eeti,egalax_ts";
249*4882a593Smuzhiyun		reg = <0x04>;
250*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
251*4882a593Smuzhiyun		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
252*4882a593Smuzhiyun		wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
253*4882a593Smuzhiyun	};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun	touchscreen@38 {
256*4882a593Smuzhiyun		compatible = "edt,edt-ft5x06";
257*4882a593Smuzhiyun		reg = <0x38>;
258*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
259*4882a593Smuzhiyun		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
260*4882a593Smuzhiyun		wakeup-source;
261*4882a593Smuzhiyun	};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun	rtc@6f {
264*4882a593Smuzhiyun		compatible = "isil,isl1208";
265*4882a593Smuzhiyun		pinctrl-names = "default";
266*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_rtc>;
267*4882a593Smuzhiyun		reg = <0x6f>;
268*4882a593Smuzhiyun		interrupts-extended = <&gpio2 26 IRQ_TYPE_LEVEL_LOW>;
269*4882a593Smuzhiyun	};
270*4882a593Smuzhiyun};
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun&iomuxc {
273*4882a593Smuzhiyun	pinctrl-names = "default";
274*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_j10>;
275*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_j28>;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun	imx6dl-nit6xlite {
278*4882a593Smuzhiyun		pinctrl_audmux: audmuxgrp {
279*4882a593Smuzhiyun			fsl,pins = <
280*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
281*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
282*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
283*4882a593Smuzhiyun				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
284*4882a593Smuzhiyun			>;
285*4882a593Smuzhiyun		};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun		pinctrl_ecspi1: ecspi1grp {
288*4882a593Smuzhiyun			fsl,pins = <
289*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
290*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
291*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
292*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x000b1
293*4882a593Smuzhiyun			>;
294*4882a593Smuzhiyun		};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun		pinctrl_enet: enetgrp {
297*4882a593Smuzhiyun			fsl,pins = <
298*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
299*4882a593Smuzhiyun				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
300*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
301*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
302*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
303*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
304*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
305*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
306*4882a593Smuzhiyun				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
307*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
308*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
309*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
310*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
311*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
312*4882a593Smuzhiyun				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
313*4882a593Smuzhiyun				/* Phy reset */
314*4882a593Smuzhiyun				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x0f0b0
315*4882a593Smuzhiyun				MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
316*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
317*4882a593Smuzhiyun			>;
318*4882a593Smuzhiyun		};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun		pinctrl_gpio_keys: gpio-keysgrp {
321*4882a593Smuzhiyun			fsl,pins = <
322*4882a593Smuzhiyun				/* Home Button: J14 pin 5 */
323*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b0
324*4882a593Smuzhiyun				/* Back Button: J14 pin 7 */
325*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0
326*4882a593Smuzhiyun			>;
327*4882a593Smuzhiyun		};
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun		pinctrl_i2c1: i2c1grp {
330*4882a593Smuzhiyun			fsl,pins = <
331*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D21__I2C1_SCL	0x4001b8b1
332*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D28__I2C1_SDA	0x4001b8b1
333*4882a593Smuzhiyun			>;
334*4882a593Smuzhiyun		};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun		pinctrl_i2c2: i2c2grp {
337*4882a593Smuzhiyun			fsl,pins = <
338*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL3__I2C2_SCL	0x4001b8b1
339*4882a593Smuzhiyun				MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
340*4882a593Smuzhiyun			>;
341*4882a593Smuzhiyun		};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun		pinctrl_i2c3: i2c3grp {
344*4882a593Smuzhiyun			fsl,pins = <
345*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_5__I2C3_SCL	0x4001b8b1
346*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_16__I2C3_SDA	0x4001b8b1
347*4882a593Smuzhiyun				/* Touch IRQ: J7 pin 4 */
348*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_9__GPIO1_IO09	0x1b0b0
349*4882a593Smuzhiyun				/* tcs2004 IRQ */
350*4882a593Smuzhiyun				MX6QDL_PAD_EIM_LBA__GPIO2_IO27	0x1b0b0
351*4882a593Smuzhiyun				/* tsc2004 reset */
352*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL2__GPIO4_IO10	0x0b0b0
353*4882a593Smuzhiyun			>;
354*4882a593Smuzhiyun		};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun		pinctrl_j10: j10grp {
357*4882a593Smuzhiyun			fsl,pins = <
358*4882a593Smuzhiyun				/* Broadcom WiFi module pins */
359*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x1b0b0
360*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
361*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D3__GPIO2_IO03		0x1b0b0
362*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_D4__GPIO2_IO04		0x1b0b0
363*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09	0x0b0b0
364*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x1b0b0
365*4882a593Smuzhiyun				MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT	0x000b0
366*4882a593Smuzhiyun			>;
367*4882a593Smuzhiyun		};
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun		pinctrl_j28: j28grp {
370*4882a593Smuzhiyun			fsl,pins = <
371*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0
372*4882a593Smuzhiyun			>;
373*4882a593Smuzhiyun		};
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun		pinctrl_leds: ledsgrp {
376*4882a593Smuzhiyun			fsl,pins = <
377*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x0b0b0
378*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_3__GPIO1_IO03		0x0b0b0
379*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x030b0
380*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_7__GPIO1_IO07		0x0b0b0
381*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_8__GPIO1_IO08		0x0b0b0
382*4882a593Smuzhiyun			>;
383*4882a593Smuzhiyun		};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun		pinctrl_pwm1: pwm1grp {
386*4882a593Smuzhiyun			fsl,pins = <
387*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
388*4882a593Smuzhiyun			>;
389*4882a593Smuzhiyun		};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun		pinctrl_pwm3: pwm3grp {
392*4882a593Smuzhiyun			fsl,pins = <
393*4882a593Smuzhiyun				MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
394*4882a593Smuzhiyun			>;
395*4882a593Smuzhiyun		};
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun		pinctrl_pwm4: pwm4grp {
398*4882a593Smuzhiyun			fsl,pins = <
399*4882a593Smuzhiyun				MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
400*4882a593Smuzhiyun			>;
401*4882a593Smuzhiyun		};
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun		pinctrl_wlan_vmmc: wlan-vmmcgrp {
404*4882a593Smuzhiyun			fsl,pins = <
405*4882a593Smuzhiyun				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07	0x030b0
406*4882a593Smuzhiyun			>;
407*4882a593Smuzhiyun		};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun		pinctrl_rtc: rtcgrp {
410*4882a593Smuzhiyun			fsl,pins = <
411*4882a593Smuzhiyun				MX6QDL_PAD_EIM_RW__GPIO2_IO26		0x1b0b0
412*4882a593Smuzhiyun			>;
413*4882a593Smuzhiyun		};
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun		pinctrl_sgtl5000: sgtl5000grp {
416*4882a593Smuzhiyun			fsl,pins = <
417*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x000b0
418*4882a593Smuzhiyun				MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b0
419*4882a593Smuzhiyun			>;
420*4882a593Smuzhiyun		};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun		pinctrl_uart1: uart1grp {
423*4882a593Smuzhiyun			fsl,pins = <
424*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
425*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
426*4882a593Smuzhiyun			>;
427*4882a593Smuzhiyun		};
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun		pinctrl_uart2: uart2grp {
430*4882a593Smuzhiyun			fsl,pins = <
431*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
432*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
433*4882a593Smuzhiyun			>;
434*4882a593Smuzhiyun		};
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun		pinctrl_uart3: uart3grp {
437*4882a593Smuzhiyun			fsl,pins = <
438*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
439*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
440*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
441*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D31__UART3_RTS_B		0x1b0b1
442*4882a593Smuzhiyun			>;
443*4882a593Smuzhiyun		};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun		pinctrl_usbotg: usbotggrp {
446*4882a593Smuzhiyun			fsl,pins = <
447*4882a593Smuzhiyun				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
448*4882a593Smuzhiyun				MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x1b0b0
449*4882a593Smuzhiyun				/* power enable, high active */
450*4882a593Smuzhiyun				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x000b0
451*4882a593Smuzhiyun			>;
452*4882a593Smuzhiyun		};
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun		pinctrl_usdhc2: usdhc2grp {
455*4882a593Smuzhiyun			fsl,pins = <
456*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
457*4882a593Smuzhiyun				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
458*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
459*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
460*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
461*4882a593Smuzhiyun				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
462*4882a593Smuzhiyun			>;
463*4882a593Smuzhiyun		};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun		pinctrl_usdhc3: usdhc3grp {
466*4882a593Smuzhiyun			fsl,pins = <
467*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
468*4882a593Smuzhiyun				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
469*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
470*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
471*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
472*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
473*4882a593Smuzhiyun				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0
474*4882a593Smuzhiyun			>;
475*4882a593Smuzhiyun		};
476*4882a593Smuzhiyun	};
477*4882a593Smuzhiyun};
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun&ldb {
480*4882a593Smuzhiyun	status = "okay";
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun	lvds-channel@0 {
483*4882a593Smuzhiyun		status = "okay";
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun		port@4 {
486*4882a593Smuzhiyun			reg = <4>;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun			lvds0_out: endpoint {
489*4882a593Smuzhiyun				remote-endpoint = <&panel_in_lvds0>;
490*4882a593Smuzhiyun			};
491*4882a593Smuzhiyun		};
492*4882a593Smuzhiyun	};
493*4882a593Smuzhiyun};
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun&pcie {
496*4882a593Smuzhiyun	status = "okay";
497*4882a593Smuzhiyun};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun&pwm1 {
500*4882a593Smuzhiyun	#pwm-cells = <2>;
501*4882a593Smuzhiyun	pinctrl-names = "default";
502*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm1>;
503*4882a593Smuzhiyun	status = "okay";
504*4882a593Smuzhiyun};
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun&pwm3 {
507*4882a593Smuzhiyun	pinctrl-names = "default";
508*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm3>;
509*4882a593Smuzhiyun	status = "okay";
510*4882a593Smuzhiyun};
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun&pwm4 {
513*4882a593Smuzhiyun	#pwm-cells = <2>;
514*4882a593Smuzhiyun	pinctrl-names = "default";
515*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_pwm4>;
516*4882a593Smuzhiyun	status = "okay";
517*4882a593Smuzhiyun};
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun&ssi1 {
520*4882a593Smuzhiyun	status = "okay";
521*4882a593Smuzhiyun};
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun&uart1 {
524*4882a593Smuzhiyun	pinctrl-names = "default";
525*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
526*4882a593Smuzhiyun	status = "okay";
527*4882a593Smuzhiyun};
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun&uart2 {
530*4882a593Smuzhiyun	pinctrl-names = "default";
531*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
532*4882a593Smuzhiyun	status = "okay";
533*4882a593Smuzhiyun};
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun&uart3 {
536*4882a593Smuzhiyun	pinctrl-names = "default";
537*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
538*4882a593Smuzhiyun	uart-has-rtscts;
539*4882a593Smuzhiyun	status = "okay";
540*4882a593Smuzhiyun};
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun&usbh1 {
543*4882a593Smuzhiyun	status = "okay";
544*4882a593Smuzhiyun};
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun&usbotg {
547*4882a593Smuzhiyun	vbus-supply = <&reg_usb_otg_vbus>;
548*4882a593Smuzhiyun	pinctrl-names = "default";
549*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usbotg>;
550*4882a593Smuzhiyun	disable-over-current;
551*4882a593Smuzhiyun	status = "okay";
552*4882a593Smuzhiyun};
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun&usdhc2 {
555*4882a593Smuzhiyun	pinctrl-names = "default";
556*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
557*4882a593Smuzhiyun	bus-width = <4>;
558*4882a593Smuzhiyun	non-removable;
559*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
560*4882a593Smuzhiyun	vqmmc-supply = <&reg_wlan_vmmc>;
561*4882a593Smuzhiyun	cap-power-off-card;
562*4882a593Smuzhiyun	keep-power-in-suspend;
563*4882a593Smuzhiyun	status = "okay";
564*4882a593Smuzhiyun};
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun&usdhc3 {
567*4882a593Smuzhiyun	pinctrl-names = "default";
568*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc3>;
569*4882a593Smuzhiyun	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
570*4882a593Smuzhiyun	vmmc-supply = <&reg_3p3v>;
571*4882a593Smuzhiyun	status = "okay";
572*4882a593Smuzhiyun};
573