1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2019 Gateworks Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 7*4882a593Smuzhiyun#include <dt-bindings/input/linux-event-codes.h> 8*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun /* these are used by bootloader for disabling nodes */ 12*4882a593Smuzhiyun aliases { 13*4882a593Smuzhiyun led0 = &led0; 14*4882a593Smuzhiyun led1 = &led1; 15*4882a593Smuzhiyun nand = &gpmi; 16*4882a593Smuzhiyun usb0 = &usbh1; 17*4882a593Smuzhiyun usb1 = &usbotg; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun chosen { 21*4882a593Smuzhiyun stdout-path = &uart2; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun gpio-keys { 25*4882a593Smuzhiyun compatible = "gpio-keys"; 26*4882a593Smuzhiyun #address-cells = <1>; 27*4882a593Smuzhiyun #size-cells = <0>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun user-pb { 30*4882a593Smuzhiyun label = "user_pb"; 31*4882a593Smuzhiyun gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; 32*4882a593Smuzhiyun linux,code = <BTN_0>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun user-pb1x { 36*4882a593Smuzhiyun label = "user_pb1x"; 37*4882a593Smuzhiyun linux,code = <BTN_1>; 38*4882a593Smuzhiyun interrupt-parent = <&gsc>; 39*4882a593Smuzhiyun interrupts = <0>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun key-erased { 43*4882a593Smuzhiyun label = "key-erased"; 44*4882a593Smuzhiyun linux,code = <BTN_2>; 45*4882a593Smuzhiyun interrupt-parent = <&gsc>; 46*4882a593Smuzhiyun interrupts = <1>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun eeprom-wp { 50*4882a593Smuzhiyun label = "eeprom_wp"; 51*4882a593Smuzhiyun linux,code = <BTN_3>; 52*4882a593Smuzhiyun interrupt-parent = <&gsc>; 53*4882a593Smuzhiyun interrupts = <2>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun tamper { 57*4882a593Smuzhiyun label = "tamper"; 58*4882a593Smuzhiyun linux,code = <BTN_4>; 59*4882a593Smuzhiyun interrupt-parent = <&gsc>; 60*4882a593Smuzhiyun interrupts = <5>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun switch-hold { 64*4882a593Smuzhiyun label = "switch_hold"; 65*4882a593Smuzhiyun linux,code = <BTN_5>; 66*4882a593Smuzhiyun interrupt-parent = <&gsc>; 67*4882a593Smuzhiyun interrupts = <7>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun leds { 72*4882a593Smuzhiyun compatible = "gpio-leds"; 73*4882a593Smuzhiyun pinctrl-names = "default"; 74*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_leds>; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun led0: user1 { 77*4882a593Smuzhiyun label = "user1"; 78*4882a593Smuzhiyun gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 79*4882a593Smuzhiyun default-state = "on"; 80*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun led1: user2 { 84*4882a593Smuzhiyun label = "user2"; 85*4882a593Smuzhiyun gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 86*4882a593Smuzhiyun default-state = "off"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun memory@10000000 { 91*4882a593Smuzhiyun device_type = "memory"; 92*4882a593Smuzhiyun reg = <0x10000000 0x20000000>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun pps { 96*4882a593Smuzhiyun compatible = "pps-gpio"; 97*4882a593Smuzhiyun pinctrl-names = "default"; 98*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pps>; 99*4882a593Smuzhiyun gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 100*4882a593Smuzhiyun status = "okay"; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun reg_3p3v: regulator-3p3v { 104*4882a593Smuzhiyun compatible = "regulator-fixed"; 105*4882a593Smuzhiyun regulator-name = "3P3V"; 106*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 107*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 108*4882a593Smuzhiyun regulator-always-on; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun reg_5p0v: regulator-5p0v { 112*4882a593Smuzhiyun compatible = "regulator-fixed"; 113*4882a593Smuzhiyun regulator-name = "5P0V"; 114*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 115*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 116*4882a593Smuzhiyun regulator-always-on; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun}; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun&fec { 121*4882a593Smuzhiyun pinctrl-names = "default"; 122*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_enet>; 123*4882a593Smuzhiyun phy-mode = "rgmii-id"; 124*4882a593Smuzhiyun status = "okay"; 125*4882a593Smuzhiyun}; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun&gpmi { 128*4882a593Smuzhiyun pinctrl-names = "default"; 129*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpmi_nand>; 130*4882a593Smuzhiyun status = "okay"; 131*4882a593Smuzhiyun}; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun&i2c1 { 134*4882a593Smuzhiyun clock-frequency = <100000>; 135*4882a593Smuzhiyun pinctrl-names = "default"; 136*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1>; 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun gsc: gsc@20 { 140*4882a593Smuzhiyun compatible = "gw,gsc"; 141*4882a593Smuzhiyun reg = <0x20>; 142*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 143*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 144*4882a593Smuzhiyun interrupt-controller; 145*4882a593Smuzhiyun #interrupt-cells = <1>; 146*4882a593Smuzhiyun #size-cells = <0>; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun adc { 149*4882a593Smuzhiyun compatible = "gw,gsc-adc"; 150*4882a593Smuzhiyun #address-cells = <1>; 151*4882a593Smuzhiyun #size-cells = <0>; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun channel@6 { 154*4882a593Smuzhiyun gw,mode = <0>; 155*4882a593Smuzhiyun reg = <0x06>; 156*4882a593Smuzhiyun label = "temp"; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun channel@8 { 160*4882a593Smuzhiyun gw,mode = <3>; 161*4882a593Smuzhiyun reg = <0x08>; 162*4882a593Smuzhiyun label = "vdd_bat"; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun channel@82 { 166*4882a593Smuzhiyun gw,mode = <2>; 167*4882a593Smuzhiyun reg = <0x82>; 168*4882a593Smuzhiyun label = "vdd_vin"; 169*4882a593Smuzhiyun gw,voltage-divider-ohms = <22100 1000>; 170*4882a593Smuzhiyun gw,voltage-offset-microvolt = <800000>; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun channel@84 { 174*4882a593Smuzhiyun gw,mode = <2>; 175*4882a593Smuzhiyun reg = <0x84>; 176*4882a593Smuzhiyun label = "vdd_5p0"; 177*4882a593Smuzhiyun gw,voltage-divider-ohms = <22100 10000>; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun channel@86 { 181*4882a593Smuzhiyun gw,mode = <2>; 182*4882a593Smuzhiyun reg = <0x86>; 183*4882a593Smuzhiyun label = "vdd_3p3"; 184*4882a593Smuzhiyun gw,voltage-divider-ohms = <10000 10000>; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun channel@88 { 188*4882a593Smuzhiyun gw,mode = <2>; 189*4882a593Smuzhiyun reg = <0x88>; 190*4882a593Smuzhiyun label = "vdd_2p5"; 191*4882a593Smuzhiyun gw,voltage-divider-ohms = <10000 10000>; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun channel@8c { 195*4882a593Smuzhiyun gw,mode = <2>; 196*4882a593Smuzhiyun reg = <0x8c>; 197*4882a593Smuzhiyun label = "vdd_arm"; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun channel@8e { 201*4882a593Smuzhiyun gw,mode = <2>; 202*4882a593Smuzhiyun reg = <0x8e>; 203*4882a593Smuzhiyun label = "vdd_soc"; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun channel@90 { 207*4882a593Smuzhiyun gw,mode = <2>; 208*4882a593Smuzhiyun reg = <0x90>; 209*4882a593Smuzhiyun label = "vdd_1p5"; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun channel@92 { 213*4882a593Smuzhiyun gw,mode = <2>; 214*4882a593Smuzhiyun reg = <0x92>; 215*4882a593Smuzhiyun label = "vdd_1p0"; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun channel@98 { 219*4882a593Smuzhiyun gw,mode = <2>; 220*4882a593Smuzhiyun reg = <0x98>; 221*4882a593Smuzhiyun label = "vdd_3p0"; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun channel@9a { 225*4882a593Smuzhiyun gw,mode = <2>; 226*4882a593Smuzhiyun reg = <0x9a>; 227*4882a593Smuzhiyun label = "vdd_an1"; 228*4882a593Smuzhiyun gw,voltage-divider-ohms = <10000 10000>; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun channel@a2 { 232*4882a593Smuzhiyun gw,mode = <2>; 233*4882a593Smuzhiyun reg = <0xa2>; 234*4882a593Smuzhiyun label = "vdd_gsc"; 235*4882a593Smuzhiyun gw,voltage-divider-ohms = <10000 10000>; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun gsc_gpio: gpio@23 { 241*4882a593Smuzhiyun compatible = "nxp,pca9555"; 242*4882a593Smuzhiyun reg = <0x23>; 243*4882a593Smuzhiyun gpio-controller; 244*4882a593Smuzhiyun #gpio-cells = <2>; 245*4882a593Smuzhiyun interrupt-parent = <&gsc>; 246*4882a593Smuzhiyun interrupts = <4>; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun eeprom@50 { 250*4882a593Smuzhiyun compatible = "atmel,24c02"; 251*4882a593Smuzhiyun reg = <0x50>; 252*4882a593Smuzhiyun pagesize = <16>; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun eeprom@51 { 256*4882a593Smuzhiyun compatible = "atmel,24c02"; 257*4882a593Smuzhiyun reg = <0x51>; 258*4882a593Smuzhiyun pagesize = <16>; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun eeprom@52 { 262*4882a593Smuzhiyun compatible = "atmel,24c02"; 263*4882a593Smuzhiyun reg = <0x52>; 264*4882a593Smuzhiyun pagesize = <16>; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun eeprom@53 { 268*4882a593Smuzhiyun compatible = "atmel,24c02"; 269*4882a593Smuzhiyun reg = <0x53>; 270*4882a593Smuzhiyun pagesize = <16>; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun rtc@68 { 274*4882a593Smuzhiyun compatible = "dallas,ds1672"; 275*4882a593Smuzhiyun reg = <0x68>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun}; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun&i2c2 { 280*4882a593Smuzhiyun clock-frequency = <100000>; 281*4882a593Smuzhiyun pinctrl-names = "default"; 282*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c2>; 283*4882a593Smuzhiyun status = "okay"; 284*4882a593Smuzhiyun}; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun&i2c3 { 287*4882a593Smuzhiyun clock-frequency = <100000>; 288*4882a593Smuzhiyun pinctrl-names = "default"; 289*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c3>; 290*4882a593Smuzhiyun status = "okay"; 291*4882a593Smuzhiyun}; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun&pcie { 294*4882a593Smuzhiyun pinctrl-names = "default"; 295*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pcie>; 296*4882a593Smuzhiyun reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 297*4882a593Smuzhiyun status = "okay"; 298*4882a593Smuzhiyun}; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun&pwm2 { 301*4882a593Smuzhiyun pinctrl-names = "default"; 302*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 303*4882a593Smuzhiyun status = "disabled"; 304*4882a593Smuzhiyun}; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun&pwm3 { 307*4882a593Smuzhiyun pinctrl-names = "default"; 308*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 309*4882a593Smuzhiyun status = "disabled"; 310*4882a593Smuzhiyun}; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun&pwm4 { 313*4882a593Smuzhiyun pinctrl-names = "default"; 314*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ 315*4882a593Smuzhiyun status = "disabled"; 316*4882a593Smuzhiyun}; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun&uart1 { 319*4882a593Smuzhiyun pinctrl-names = "default"; 320*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 321*4882a593Smuzhiyun status = "okay"; 322*4882a593Smuzhiyun}; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun&uart2 { 325*4882a593Smuzhiyun pinctrl-names = "default"; 326*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart2>; 327*4882a593Smuzhiyun status = "okay"; 328*4882a593Smuzhiyun}; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun&uart3 { 331*4882a593Smuzhiyun pinctrl-names = "default"; 332*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 333*4882a593Smuzhiyun status = "okay"; 334*4882a593Smuzhiyun}; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun&uart5 { 337*4882a593Smuzhiyun pinctrl-names = "default"; 338*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart5>; 339*4882a593Smuzhiyun status = "okay"; 340*4882a593Smuzhiyun}; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun&usbotg { 343*4882a593Smuzhiyun pinctrl-names = "default"; 344*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usbotg>; 345*4882a593Smuzhiyun disable-over-current; 346*4882a593Smuzhiyun status = "okay"; 347*4882a593Smuzhiyun}; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun&usbh1 { 350*4882a593Smuzhiyun status = "okay"; 351*4882a593Smuzhiyun}; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun&wdog1 { 354*4882a593Smuzhiyun pinctrl-names = "default"; 355*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_wdog>; 356*4882a593Smuzhiyun fsl,ext-reset-output; 357*4882a593Smuzhiyun}; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun&iomuxc { 360*4882a593Smuzhiyun pinctrl_enet: enetgrp { 361*4882a593Smuzhiyun fsl,pins = < 362*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 363*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 364*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 365*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 366*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 367*4882a593Smuzhiyun MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 368*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 369*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 370*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 371*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 372*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 373*4882a593Smuzhiyun MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 374*4882a593Smuzhiyun MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 375*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 376*4882a593Smuzhiyun MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 377*4882a593Smuzhiyun MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 378*4882a593Smuzhiyun MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 379*4882a593Smuzhiyun >; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun pinctrl_gpio_leds: gpioledsgrp { 383*4882a593Smuzhiyun fsl,pins = < 384*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 385*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 386*4882a593Smuzhiyun >; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun pinctrl_gpmi_nand: gpminandgrp { 390*4882a593Smuzhiyun fsl,pins = < 391*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 392*4882a593Smuzhiyun MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 393*4882a593Smuzhiyun MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 394*4882a593Smuzhiyun MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 395*4882a593Smuzhiyun MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 396*4882a593Smuzhiyun MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 397*4882a593Smuzhiyun MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 398*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 399*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 400*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 401*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 402*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 403*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 404*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 405*4882a593Smuzhiyun MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 406*4882a593Smuzhiyun >; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun pinctrl_i2c1: i2c1grp { 410*4882a593Smuzhiyun fsl,pins = < 411*4882a593Smuzhiyun MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 412*4882a593Smuzhiyun MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 413*4882a593Smuzhiyun MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 414*4882a593Smuzhiyun >; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun pinctrl_i2c2: i2c2grp { 418*4882a593Smuzhiyun fsl,pins = < 419*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 420*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 421*4882a593Smuzhiyun >; 422*4882a593Smuzhiyun }; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun pinctrl_i2c3: i2c3grp { 425*4882a593Smuzhiyun fsl,pins = < 426*4882a593Smuzhiyun MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 427*4882a593Smuzhiyun MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 428*4882a593Smuzhiyun >; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun pinctrl_pcie: pciegrp { 432*4882a593Smuzhiyun fsl,pins = < 433*4882a593Smuzhiyun MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 434*4882a593Smuzhiyun >; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun pinctrl_pps: ppsgrp { 438*4882a593Smuzhiyun fsl,pins = < 439*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1 440*4882a593Smuzhiyun >; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun pinctrl_pwm2: pwm2grp { 444*4882a593Smuzhiyun fsl,pins = < 445*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 446*4882a593Smuzhiyun >; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun pinctrl_pwm3: pwm3grp { 450*4882a593Smuzhiyun fsl,pins = < 451*4882a593Smuzhiyun MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 452*4882a593Smuzhiyun >; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun pinctrl_pwm4: pwm4grp { 456*4882a593Smuzhiyun fsl,pins = < 457*4882a593Smuzhiyun MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 458*4882a593Smuzhiyun >; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun pinctrl_uart1: uart1grp { 462*4882a593Smuzhiyun fsl,pins = < 463*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 464*4882a593Smuzhiyun MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 465*4882a593Smuzhiyun >; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 469*4882a593Smuzhiyun fsl,pins = < 470*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 471*4882a593Smuzhiyun MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 472*4882a593Smuzhiyun >; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 476*4882a593Smuzhiyun fsl,pins = < 477*4882a593Smuzhiyun MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 478*4882a593Smuzhiyun MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 479*4882a593Smuzhiyun >; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun pinctrl_uart5: uart5grp { 483*4882a593Smuzhiyun fsl,pins = < 484*4882a593Smuzhiyun MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 485*4882a593Smuzhiyun MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 486*4882a593Smuzhiyun >; 487*4882a593Smuzhiyun }; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun pinctrl_usbotg: usbotggrp { 490*4882a593Smuzhiyun fsl,pins = < 491*4882a593Smuzhiyun MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 492*4882a593Smuzhiyun >; 493*4882a593Smuzhiyun }; 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun pinctrl_wdog: wdoggrp { 496*4882a593Smuzhiyun fsl,pins = < 497*4882a593Smuzhiyun MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 498*4882a593Smuzhiyun >; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun}; 501